參數(shù)資料
型號(hào)： LTC2483IDD#PBF
廠商： Linear Technology
文件頁數(shù)： 15/34頁
文件大小： 0K
描述： IC ADC 16BIT I2C 10-DFN
標(biāo)準(zhǔn)包裝： 121
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁面： 1348 (CN2011-ZH PDF)
配用： DC955A-ND - BOARD DELTA SIGMA ADC LTC2483
LTC2483
2483fc
Output Data Rate
When using its internal oscillator, the LTC2483 produces
up to 6.82sps with simultaneous 50Hz/60Hz rejection.
The actual output data rate will depend upon the length
of the sleep and data output phases which are controlled
by the user and which can be made insignificantly short.
When operated with an external conversion clock (CA0/F0
connected to an external oscillator), the LTC2483 output
data rate can be increased as desired. The duration of the
conversion phase is 41036/fEOSC. If fEOSC = 307.2kHz, the
converter notch is set at 60Hz.
An increase in fEOSC over the nominal 307.2kHz will
translate into a proportional increase in the maximum
applicaTions inFormaTion
Figure 16. Offset Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET
ERROR
(ppm
OF
V
REF
)
10
30
50
0
20
40
20
40
60
80
2483 F16
100
10
0
30
50
70
90
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
CA0/F0 = EXT CLOCK
TA = 85°C
TA = 25°C
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line fre-
quency.Inmanyapplications,thesubsequentperformance
degradation can be substantially reduced by relying upon
the LTC2483’s exceptional common mode rejection and by
carefully eliminating common mode to differential mode
conversion sources in the input circuit. The user should
avoid single-ended input filters and should maintain a
very high degree of matching and symmetry in the circuits
driving the IN+ and IN– pins.
Figure 17. +FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
+FS
ERROR
(ppm
OF
V
REF
)
500
1500
2000
2500
3500
10
50
70
2483 F17
1000
3000
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
CA0/F0 = EXT CLOCK
TA = 85°C
TA = 25°C
Figure 18. –FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
–3500
–FS
ERROR
(ppm
OF
V
REF
)
–3000
–2000
–1500
–1000
0
10
50
70
2483 F18
–2500
–500
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
CA0/F0 = EXT CLOCK
TA = 85°C
TA = 25°C
Figure 19. Resolution (NoiseRMS ≤ 1 LSB)
vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION
(BITS)
12
16
18
20
24
10
50
70
2483 F19
14
22
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
CA0/F0 = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
TA = 85°C
TA = 25°C
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