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參數(shù)資料
| 型號(hào)： | LTC2480HDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SRL 7.5SPS 10DFN |
| 標(biāo)準(zhǔn)包裝： | 121 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 配用： | DC798B-ND - BOARD DELTA SIGMA ADC LTC2480 |
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LTC2480
2480fd
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally gener-
ated serial clock (SCK) signal, see Figure 10. CS may be
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-upisactiveduringthePORcycle;therefore,theinternal
serial clock timing mode is automatically selected if SCK
is not externally driven LOW (if SCK is loaded such that
the internal pull-up cannot pull the pin HIGH, the external
SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has finished and the device has entered
the low power sleep state. The part remains in the sleep
state a minimum amount of time (1/2 the internal SCK
period) then immediately begins outputting data. The
data input/output cycle begins on the first rising edge of
SCK and ends after the 24th rising edge. The input data
is then shifted in via the SDI pin on the rising edge of
SCK (including the first rising edge) and the output data
is shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the first ris-
ing edge of SCK and the last bit of the conversion result
can be latched on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
Preserving the Converter Accuracy
The LTC2480 is designed to reduce as much as possible
theconversionresultsensitivitytodevicedecoupling,PCB
layout, anti-aliasing circuits, line frequency perturbations
and so on. Nevertheless, in order to preserve the 24-bit
accuracy capability of this part, some simple precautions
are required.
applicaTions inForMaTion
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SDI*
DON’T CARE
SDO
SCK
(INTERNAL)
CS
LSB
MSB
SIG
BIT 4
BIT 0
IM
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
DATA OUTPUT
CONVERSION
2480 F10
VCC
FO
VREF
IN+
IN–
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUT
1F
2.7V TO 5.5V
LTC2480
3-WIRE
SPI INTERFACE
10k
VCC
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
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