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參數(shù)資料
| 型號： | LTC2480HDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SRL 7.5SPS 10DFN |
| 標準包裝： | 121 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
| 配用： | DC798B-ND - BOARD DELTA SIGMA ADC LTC2480 |
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LTC2480
2480fd
applicaTions inForMaTion
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Table 5 summarizes the duration of each state and the
achievable output data rate as a function of fO.
Ease of Use
The LTC2480 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2480 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
theuserandhasnoeffectonthecyclicoperationdescribed
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2480 automatically enters an internal reset state
when the power supply voltage VCC drops below ap-
proximately 2V. This feature guarantees the integrity of
the conversion result and of the serial interface mode
selection.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signalclearsallinternalregisters.FollowingthePORsignal,
the LTC2480 starts a normal conversion cycle and follows
the succession of states described in Figure 1. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
On-Chip Temperature Sensor
The LTC2480 contains an on-chip PTAT (proportional to
absolutetemperature)signalthatcanbeusedasatempera-
ture sensor. The internal PTAT has a typical value of 420mV
at 27°C and is proportional to the absolute temperature
Table 5. LTC2480 State Duration
STATE
OPERATING MODE
DURATION
CONVERT
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator
fO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/5120 Rejection)
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s for
1x Speed Mode
20556/fEOSCs, Output Data Rate ≤ fEOSC/20556 Readings/s for
2x Speed Mode
SLEEP
As Long As CS = HIGH, After a Conversion is Complete
DATA OUTPUT
Internal Serial Clock
fO = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 0.62ms
(24 SCK Cycles)
fO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 192/fEOSCms
(24 SCK Cycles)
External Serial Clock with
Frequency fSCK kHz
As Long As CS = LOW But Not Longer Than 24/fSCKms
(24 SCK Cycles)
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