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參數(shù)資料
| 型號： | LTC2453ITS8#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT DELTA SIG TSOT23-8 |
| 產(chǎn)品培訓模塊： | LTC2460 and LTC2450 Delta Sigma ADC Families |
| 標準包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 60 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應商設(shè)備封裝： | TSOT-23-8 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 其它名稱： | LTC2453ITS8#TRMPBFDKR |
LTC2453
11
2453fc
Driving VCC and GND
In relation to the VCC and GND pins, the LTC2453 com-
bines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless, the
very high accuracy of this converter is best preserved by
careful low and high frequency power supply decoupling.
A 0.1F, high quality, ceramic capacitor in parallel with a
10F ceramic capacitor should be connected between the
VCC and GND pins, as close as possible to the package.
The 0.1F capacitor should be placed closest to the ADC
package. It is also desirable to avoid any via in the circuit
path, starting from the converter VCC pin, passing through
these two decoupling capacitors, and returning to the
converter GND pin. The area encompassed by this circuit
path, as well as the path length, should be minimized.
Very low impedance ground and power planes, and star
connections at both VCC and GND pins, are preferable. The
VCC pin should have three distinct connections: the first to
RSW
15k
(TYP)
ILEAK
VCC
CEQ
0.35pF
(TYP)
IN+
IN–
REF–
REF+
2453 F08
RSW
15k
(TYP)
ILEAK
RSW
15k
(TYP)
ILEAK
RSW
15k
(TYP)
ILEAK
Figure 8. LTC2453 Analog Input/Reference Equivalent Circuit
ILEAK
RSW
15k
(TYP)
ICONV
CIN
IN+
VCC
SIG+
SIG–
RS
CEQ
0.35pF
(TYP)
CPAR
+–
2453 F09
ILEAK
RSW
15k
(TYP)
ICONV
CIN
IN–
VCC
RS
CEQ
0.35pF
(TYP)
CPAR
+–
Figure 9. LTC2453 Input Drive Equivalent Circuit
the decoupling capacitors described above, the second to
the ground return for the input signal source, and the third
to the ground return for the power supply voltage source.
Driving REF+ and REF–
A simplified equivalent circuit for REF+ and REF– is shown
in Figure 8. Like all other A/D converters, the LTC2453 is
only as accurate as the reference it is using. Therefore, it
is important to keep the reference line quiet by careful low
and high frequency power supply decoupling.
The LT6660 reference is an ideal match for driving the
LTC2453’s REF+ pin. The LTC6660 is available in a 2mm
× 2mm DFN package with 2.5V, 3V, 3.3V and 5V options.
A 0.1F, high quality, ceramic capacitor in parallel with
a 10F ceramic capacitor should be connected between
the REF+/REF– and GND pins, as close as possible to the
package. The 0.1F capacitor should be placed closest
to the ADC.
Driving VIN+ and VIN–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 9. The input signal VSIG is
connected to the ADC input pins (IN+ and IN–) through
an equivalent source resistance RS. This resistor includes
both the actual generator source resistance and any ad-
ditional optional resistors connected to the input pins.
Optional input capacitors CIN are also connected to the
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