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參數(shù)資料
| 型號： | LTC2420 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Micropower 20-bit ADC(微功耗，20位串行模數(shù)轉(zhuǎn)換器) |
| 中文描述： | 微功耗20位ADC（微功耗，20位串行模數(shù)轉(zhuǎn)換器） |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 388K |
| 代理商： | LTC2420 |
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16
LTC2420
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND
CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1
μ
F
2.7V TO 5.5V
LTC2420
TEST EOC
MSB
LSB
20
EXR
SIG
BIT 0
BIT 4
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
SLEEP
DATA OUTPUT
CONVERSION
2420 F06
CONVERSION
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
Hi-Z
Hi-Z
Hi-Z
V
CC
TEST EOC
TEST EOC
APPLICATIU
W
U
U
Figure 6. External Serial Clock, Single Cycle Operation
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
24th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 24 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 8. CS
may be permanently tied to ground (Pin 4), simplifying the
user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and EOC
= 0 once the conversion enters the low power sleep state.
On the falling edge of EOC, the conversion result is loaded
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