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參數(shù)資料
| 型號： | LTC2420 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Micropower 20-bit ADC(微功耗，20位串行模數(shù)轉(zhuǎn)換器) |
| 中文描述： | 微功耗20位ADC（微功耗，20位串行模數(shù)轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/36頁 |
| 文件大小： | 388K |
| 代理商： | LTC2420 |
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10
LTC2420
APPLICATIU
The LTC2420 is pin compatible with the LTC2400. The two
devices are designed to allow the user to incorporate
either device in the same design with no modifications.
While the LTC2420 output word length is 24 bits (as
opposed to the 32-bit output of the LTC2400), its output
clock timing can be identical to the LTC2400. As shown in
Figure 1, the LTC2420 data output is concluded on the
falling edge of the 24th serial clock (SCK). In order to
maintain drop-in compatibility with the LTC2400, it is
possible to clock the LTC2420 with an additional 8 serial
clock pulses. This results in 8 additional output bits which
are always logic HIGH.
W
U
U
Converter Operation Cycle
The LTC2420 is a low power, delta-sigma analog-to-
digital converter with an easy to use 3-wire serial interface.
Its operation is simple and made up of three states. The
converter operating cycle begins with the conversion,
followed by a low power sleep state and concluded with
the data output (see Figure 2). The 3-wire interface con-
sists of serial data output (SDO), a serial clock (SCK) and
a chip select (CS).
Initially, the LTC2420 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced by
an order of magnitude. The part remains in the sleep state
as long as CS is logic HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK, see Figure 4.
The data output state is concluded once 24 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion cycle and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2420 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require
program
ming configuration registers; moreover, they do
Figure 1. LTC2420 Compatible Timing with the LTC2400
CS
SCK
SDO
CONVERSION
SLEEP
8
8
8
8 (OPTIONAL)
EOC = 1
EOC = 1
LAST 8 BITS ALWAYS 1
EOC = 0
DATA OUT
4 STATUS BITS 20 DATA BITS
DATA OUTPUT
2420 F01
CONVERSION
CONVERT
SLEEP
DATA OUTPUT
2420 F02
0
1
CS AND
SCK
Figure 2. LTC2420 State Transition Diagram
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| LTC2420CS8#PBF | 制造商:Linear Technology 功能描述:A/D Converter (A-D) IC |
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