參數(shù)資料
型號(hào)： LTC2411CMS
英文描述： Analog-to-Digital Converter， 24-Bit
中文描述： 模擬到數(shù)字轉(zhuǎn)換器，24比特
文件頁(yè)數(shù)： 6/40頁(yè)
文件大?。?/td> 450K
代理商： LTC2411CMS
LTC2411
14
As long as the voltage on the IN+ and IN– pins is maintained
within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF to
+FS = 0.5 VREF. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Frequency Rejection Selection (FO)
The LTC2411 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz
±2% or 60Hz ±2%. For 60Hz rejec-
tion, FO should be connected to GND while for 50Hz
rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2411 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2411 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2411
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
SERIAL INTERFACE PINS
The LTC2411 transmits the conversion results and re-
ceives the start of conversion command through a syn-
chronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Figure 4. LTC2411 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
–12
–8
–4
048
12
NORMAL
MODE
REJECTION
(dB)
2411 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
APPLICATIO S I FOR ATIO
WU
UU
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