參數(shù)資料
型號(hào)： LTC2411CMS
英文描述： Analog-to-Digital Converter， 24-Bit
中文描述： 模擬到數(shù)字轉(zhuǎn)換器，24比特
文件頁(yè)數(shù)： 17/40頁(yè)
文件大?。?/td> 450K
代理商： LTC2411CMS
LTC2411
24
Larger values of input capacitors (CIN > 0.01F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 5.4M
which will
generate a gain error of approximately 0.093ppm for each
ohm of source resistance driving IN+ or IN–. When FO =
HIGH (internal oscillator and 50Hz notch), the typical
differential input resistance is 6.5M
which will generate
a gain error of approximately 0.077ppm for each ohm of
source resistance driving IN+ or IN–. When FO is driven by
an external oscillator with a frequency fEOSC (external
conversion clock operation), the typical differential input
resistance is 0.83 1012/fEOSC and each ohm of
source resistance driving IN+ or IN– will result in
0.59 10–6 fEOSCppm gain error. The effect of the source
resistance on the two input pins is additive with respect to
this gain error. The typical +FS and –FS errors as a function
of the sum of the source resistance seen by IN+ and IN– for
large values of CIN are shown in Figure 15.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN+ and IN– pins. When FO = LOW
(internal oscillator and 60Hz notch), every 1
mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.093ppm. When FO = HIGH (internal oscillator and 50Hz
notch), every 1
mismatch in source impedance trans-
forms a full-scale common mode input signal into a
differential mode input signal of 0.077ppm. When FO is
driven by an external oscillator with a frequency fEOSC,
every 1
mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 0.59 10–6 fEOSCppm. Figure 16
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN+ and IN– pins when large CIN values are
used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
APPLICATIO S I FOR ATIO
WU
UU
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
+FS
ERROR
(ppm
OF
V
REF
)
2411 F15a
120
100
80
60
40
20
0
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CIN = 1F
CIN = 0.1F
CIN = 0.01F
CIN = 10F
Figure 15a. + FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 15b. – FS Error vs RSOURCE at IN+ or IN– (Large CIN)
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
–
FS
ERROR
(ppm
OF
V
REF
)
2411 F15b
–120
–100
–80
–60
–40
–20
0
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CIN = 1F
CIN = 0.1F
CIN = 0.01F
CIN = 10F
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