參數(shù)資料
型號(hào)： LTC2411CMS
英文描述： Analog-to-Digital Converter， 24-Bit
中文描述： 模擬到數(shù)字轉(zhuǎn)換器，24比特
文件頁數(shù)： 40/40頁
文件大?。?/td> 450K
代理商： LTC2411CMS
LTC2411
9
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Offset Error vs Output Data Rate
Resolution (NOISERMS ≤ 1LSB)
vs Output Data Rate
OUTPUT DATA RATE (READINGS/SEC)
–120
OFFSET
ERROR
(ppm
OF
V
REF
)
–60
–20
40
–80
–100
–40
20
0
20
40
60
80
2411 G28
100
10
030
50
70
90
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
TA = 25°C
VREF = 2.5V
VREF = 5V
OUTPUT DATA RATE (READINGS/SEC)
0
RESOLUTION
(BITS)
20
21
80
2411 G29
19
18
20
40 50
100
22
60
10
30
90
70
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/NOISERMS)
TA = 25°C
VREF = 2.5V
VREF = 5V
Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION
(BITS)
14
18
22
12
16
20
40
60
80
2411 G30
100
10
030
50
70
90
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/INLMAX)
TA = 25°C
VREF = 2.5V
VREF = 5V
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10
F tantalum capacitor in parallel with
0.1
F ceramic capacitor as close to the part as possible.
REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF+, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits the
converter bipolar input range (VIN = IN+ – IN–) extends
from – 0.5 (VREF) to 0.5 (VREF). Outside this input range
the converter produces unique overrange and underrange
output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 8): Three-State Digital Output. During the Data
Output period this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC) the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial
interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
UU
U
PI FU CTIO S
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