參數(shù)資料
型號: LTC2274IUJ
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
封裝: 6 X 6 MM, PLASTIC, QFN-40
文件頁數(shù): 17/40頁
文件大?。?/td> 897K
代理商: LTC2274IUJ
LTC2274
24
2274fb
APPLICATIONS INFORMATION
Initial Frame Synchronization
In the absence of a frame clock, it is necessary to deter-
mine the start of each frame through a synchronization
process. To establish frame synchronization, Figures 14
and 15 illustrate the following sequence:
The receiver issues a synchronization request via the
synchronization interface.
If the synchronization request is active for more than
one ENC clock cycle, the LTC2274 will transmit a
synchronization preamble. When the ISMODE pin is
low the transmitted preamble will consist of consecu-
tive K28.5 comma symbols in conformance with the
JESD204 specication. When the ISMODE pin is high,
a series of idle ordered sets will be transmitted. The
idle ordered sets consist of a K28.5 comma followed by
either D5.6 or D16.2 as dened in IEEE Std 802.3-2002
part3, Clause 36.2.4.12.
The receiver searches for the expected preamble and
waits for the correct reception of an adequate number
of preamble characters.
The receiver deactivates the synchronization request.
Upon detecting the deactivation of the synchroniza-
tion request, the LTC2274 continues to transmit the
synchronization preamble until the end of the frame.
At the start of the next frame, the LTC2274 will begin
transmitting data characters.
The receiver designates the rst data character received
after the preamble transmission to be the start of the
frame. The rst octet of the frame contains the most
signicant byte of the ADC’s output word.
Figure 13. Timing Relationship of Analog Sample to Serial Data Out
N – 6
N – 10
N – 9
N – 8
N – 1
N
N – 5
N – 4
N + 3
N + 4
N – 9
N – 8
N – 7
N
N + 1
tH
tCONV
LATP
tL
tAP
tBIT
N
N + 1
N + 2
N + 8
N + 9
2274 F13
N + 10
ANALOG INPUT
ENC+
INTERNAL
PARALLEL DATA
INTERNAL
8B/10B DATA
SERIAL DATA OUT
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