參數(shù)資料
型號： LTC2268IUJ-14#TRPBF
廠商： Linear Technology
文件頁數(shù)： 19/32頁
文件大小： 0K
描述： IC ADC 14BIT 125MSPS DUAL 40QFN
標準包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 364mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應商設備封裝： 40-QFN（6x6）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 Differential; 2 Single-Ended
配用： DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2268-14/
LTC2267-14/LTC2266-14
26
22687614fa
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE2
OUTMODE1
OUTMODE0
Bits 7-5
ILVDS2:ILVDS0
LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 4
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0. Internal termination should only be
used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Bit 3
OUTOFF
Output Disable Bit
0 = Digital Outputs are enabled.
1 = Digital Outputs are disabled.
Bits 2-0
OUTMODE2:OUTMODE0 Digital Output Mode Control Bits
000 = 2-Lanes, 16-Bit Serialization
001 = 2-Lanes, 14-Bit Serialization
010 = 2-Lanes, 12-Bit Serialization
011 = Not Used
100 = Not Used
101 = 1-Lane, 14-Bit Serialization
110 = 1-Lane, 12-Bit Serialization
111 = 1-Lane, 16-Bit Serialization
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
D0
OUTTEST
X
TP13
TP12
TP11
TP10
TP9
TP8
Bit 7
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bit 6
Unused, Don’t Care Bit.
Bits 5-0
TP13:TP8
Test Pattern Data Bits (MSB)
TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Bits 7-0
TP7:TP0
Test Pattern Data Bits (LSB)
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
applicaTions inForMaTion
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