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參數(shù)資料
| 型號： | LTC2230 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit Universal Bus Driver With 3-State Outputs 48-TVSOP -40 to 85 |
| 中文描述： | 除電氣規(guī)格更改 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 695K |
| 代理商： | LTC2230 |
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LTC2230/LTC2231
21
22301p
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
DD
or 2/3V
DD
using external resistors.
The lower limit of the LTC2230/LTC2231 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2230/LTC2231 is 1Msps.
connected to GND, 1/3V
DD
, 2/3V
DD
or V
DD
. An external
resistor divider can be used to set the 1/3V
DD
or 2/3V
DD
logic values. Table 1 shows the logic states for the
LVDS pin.
Table 1. LVDS Pin Function
LVDS
Digital Output Mode
GND
Full-Rate CMOS
1/3V
DD
Demultiplexed CMOS, Simultaneous Update
2/3V
DD
Demultiplexed CMOS, Interleaved Update
V
DD
LVDS
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single output
buffer in the CMOS output mode. Each buffer is powered
by OV
DD
and OGND, isolated from the ADC power and
ground. The additional N-channel transistor in the output
driver allows operation down to low voltages. The internal
resistor in series with the output makes the output appear
as 50
to external circuitry and may eliminate the need for
external damping resistors.
APPLICATIOU
W
U
U
DIGITAL OUTPUTS
Digital Output Modes
The LTC2230/LTC2231 can operate in several digital out-
put modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should be
22301 F12a
ENC
–
1.6V
V
THRESHOLD
= 1.6V
ENC
+
0.1
μ
F
LTC2230/
LTC2231
22301 F12b
ENC
–
ENC
+
130
3.3V
3.3V
130
Q0
D0
Q0
MC100LVELT22
LTC2230/
LTC2231
83
83
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
LTC2230/LTC2231
22301 F13a
OV
DD
V
DD
V
DD
0.1
μ
F
43
TYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO V
DD
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 13a. Digital Output Buffer in CMOS Mode
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2230/LTC2231 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. The
output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
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| LTC2232 | 16-Bit Universal Bus Driver With 3-State Outputs 48-TSSOP -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2230_1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit,170Msps/135Msps ADCs |
| LTC2230CUP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit,170Msps/135Msps ADCs |
| LTC2230CUP#PBF | 功能描述:IC ADC 10BIT 170MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2230CUP#TRPBF | 功能描述:IC ADC 10BIT 170MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2230IUP | 制造商:Linear Technology 功能描述:ADC Single Pipelined 170Msps 10-bit Parallel 64-Pin QFN EP |
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