- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377768 > LTC2230 (Linear Technology Corporation) 16-Bit Universal Bus Driver With 3-State Outputs 48-TVSOP -40 to 85 PDF資料下載
參數(shù)資料
| 型號： | LTC2230 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit Universal Bus Driver With 3-State Outputs 48-TVSOP -40 to 85 |
| 中文描述： | 除電氣規(guī)格更改 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 695K |
| 代理商： | LTC2230 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
LTC2230/LTC2231
12
22301p
(CMOS Mode)
A
IN+
(Pins 1, 2):
Positive Differential Analog Input.
A
IN–
(Pins 3, 4):
Negative Differential Analog Input.
REFHA (Pins 5, 6):
ADC High Reference. Bypass to
Pins 7, 8 with 0.1
μ
F ceramic chip capacitor, to Pins 11, 12
with a 2.2
μ
F ceramic capacitor and to ground with 1
μ
F
ceramic capacitor.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins 5,
6 with 0.1
μ
F ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10):
ADC High Reference. Bypass to
Pins 11, 12 with 0.1
μ
F ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to
Pins 9, 10 with 0.1
μ
F ceramic chip capacitor, to Pins 5, 6
with a 2.2
μ
F ceramic capacitor and to ground with 1
μ
F
ceramic capacitor.
V
DD
(Pins 13, 14, 15, 62, 63):
3.3V Supply. Bypass to
GND with 0.1
μ
F ceramic chip capacitors.
GND (Pins 16, 61, 64):
ADC Power Ground.
ENC
+
(Pin 17):
Encode Input. The input sample starts on
the positive edge.
ENC
–
(Pin 18):
Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1
μ
F
ceramic for single-ended ENCODE signal.
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
DD
results in normal operation with the
outputs at high impedance. Connecting SHDN to V
DD
and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode with the outputs at high impedance.
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin
function.
DNC (Pins 21, 22, 40, 43):
Do not connect these pins.
DB0 - DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36):
Digital Outputs, B bus. At high impedance in full rate
CMOS mode. DB9 is MSB.
OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
OV
DD
(Pins 26, 34, 42, 49):
Positive Supply for the Output
Drivers. Bypass to ground with 0.1
μ
F ceramic chip
capacitor.
OFB (Pin 37):
Over/Under Flow Output for B bus. High
when an over or under flow has occurred. At high imped-
ance in full rate CMOS mode.
CLKOUTB (Pin 38):
Data Valid Output for B bus. In demux
mode with interleaved update, latch B bus data on the
falling edge of CLKOUTB. In demux mode with simulta-
neous update, latch B bus data on the rising edge of
CLKOUTB. This pin does not become high impedance in
full rate CMOS mode.
CLKOUTA (Pin 39):
Data Valid Output for A bus. Latch A
bus data on the falling edge of CLKOUTA.
DA0 - DA9 (Pins 44 to 48, 51 to 55):
Digital Outputs, A bus.
DA9 is the MSB.
OFA (Pin 56):
Over/Under Flow Output for A bus. High
when an over or under flow has occurred.
LVDS (Pin 57):
Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3V
DD
selects demux CMOS mode with simulta-
neous update. Connecting LVDS to 2/3V
DD
selects demux
CMOS mode with interleaved update. Connecting LVDS to
V
DD
selects LVDS mode.
MODE (Pin 58):
Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
straight binary output format and turns the clock duty
cycle stabilizer off. Connecting MODE to 1/3V
DD
selects
straight binary output format and turns the clock duty
cycle stabilizer on. Connecting MODE to 2/3V
DD
selects
2’s complement output format and turns the clock duty
cycle stabilizer on. Connecting MODE to V
DD
selects 2’s
complement output format and turns the clock duty cycle
stabilizer off.
PIU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2231 | 16-Bit Universal Bus Driver With 3-State Outputs 48-SSOP -40 to 85 |
| LTC2230CUP | Electrical Specifications Subject to Change |
| LTC2231IUP | Electrical Specifications Subject to Change |
| LTC2232 | 16-Bit Universal Bus Driver With 3-State Outputs 48-TSSOP -40 to 85 |
| LTC2249IUH | 14-Bit, 80Msps Low Power 3V ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2230_1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit,170Msps/135Msps ADCs |
| LTC2230CUP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit,170Msps/135Msps ADCs |
| LTC2230CUP#PBF | 功能描述:IC ADC 10BIT 170MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2230CUP#TRPBF | 功能描述:IC ADC 10BIT 170MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2230IUP | 制造商:Linear Technology 功能描述:ADC Single Pipelined 170Msps 10-bit Parallel 64-Pin QFN EP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。