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參數(shù)資料
| 型號： | LTC2209IUP |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 593K |
| 代理商： | LTC2209IUP |
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LTC2209
23
2209fb
resistor, even if the signal is not used (such as OF+/OF–
or CLKOUT+/CLKOUT–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100 termination resistor. The output common
mode voltage is 1.20V, the same as standard LVDS Mode.
Data Format
TheLTC2209paralleldigitaloutputcanbeselectedforoffset
binary or 2’s complement format. The format is selected
with the MODE pin. This pin has a four level logic input,
centered at 0, 1/3VDD, 2/3VDD and VDD. An external resis-
tor divider can be user to set the 1/3VDD and 2/3VDD logic
levels. Table 2 shows the logic states for the MODE pin.
Table 2. MODE Pin Function
MODE
Output Format
Clock Duty
Cycle Stabilizer
0V(GND)
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Figure 11. Equivalent Circuit for a Digital Output Buffer
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers (LVDS Modes)
Figure 12 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT+ to OUT– or
vice versa, which creates a ±350mV differential voltage
across the 100 termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt-
age to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100 termination
Figure 12. Equivalent Output Buffer in LVDS Mode
applications inForMation
LTC2209
2209 F11
OVDD
VDD
0.1F
TYPICAL
DATA
OUTPUT
OGND
OVDD 0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
43
LTC2209
2209 F12
3.5mA
1.20V
LVDS
RECEIVER
OGND
10k
VDD
0.1F
OVDD
3.3V
PREDRIVER
LOGIC
DATA
FROM
LATCH
+
–
OVDD
43
100
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2209IUP#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 160Msps 16-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 160MSPS 64-QFN 制造商:Linear Technology 功能描述:IC 16BIT ADC 160MSPS 64QFN 制造商:Linear Technology 功能描述:IC, 16BIT ADC, 160MSPS, 64QFN 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 160MSPS, QFN-64; Resolution (Bits):16bit; Sampling Rate:160MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:440mA; Digital IC Case Style:QFN; No. of Pins:64 ;RoHS Compliant: Yes |
| LTC2209IUP#PBF | 制造商:Linear Technology 功能描述:A/D Converter (A-D) IC |
| LTC2209IUP#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 160Msps 16-bit Parallel/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 160MSPS 64-QFN |
| LTC2209IUP-14 | 制造商:Linear Technology 功能描述:14-BIT, 160MSPS ADC |
| LTC2209IUP-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 160Msps ADC |
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