參數(shù)資料
型號(hào)： LTC1967IMS8#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 19/28頁(yè)
文件大?。?/td> 327K
描述： IC CONVERTER RMS-DC PREC 8MSOP
標(biāo)準(zhǔn)包裝： 2,500
電流 - 電源： 320µA
電源電壓： 4.5 V ~ 5.5 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
19
LTC1967
1967f
waveform dynamics and the type of filtering used. The
above method is conservative for some cases and about
right for others.
The LTC1967 works well with signals whose crest factor
is 4 or less. At higher crest factors, the internal ?/DIV>
modulator will saturate, and results will vary depending on
the exact frequency, shape and (to a lesser extent) ampli-
tude of the input waveform. The output voltage could be
higher or lower than the actual RMS of the input signal.
The ?modulator may also saturate when signals with
crest factors less than 4 are used with insufficient averag-
ing. This will only occur when the output droops to less
than 1/4 of the input voltage peak. For instance, a DC-
coupled pulse train with a crest factor of 4 has a duty cycle
of 6.25% and a 1V
PEAK
 input is 250mV
RMS
. If this input is
50Hz, repeating every 20ms, and C
AVE
 = 1礔, the output
will droop during the inactive 93.75% of the waveform.
This droop is calculated as:
V
V
e
MIN
RMS
INACTIVETIME
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>

?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
2
1
2 " Z  " C
OUT  AVE
For the LTC1967, whose output impedance (Z
OUT
) is
50k&, this droop works out to 8.54%, so the output
would be reduced to 229mV at the end of the inactive
portion of the input. When the input signal again climbs to
1V
PEAK
, the peak/output ratio is 4.36.
With C
AVE
 = 10礔, the droop is only 0.929% to 247.7mV
and the peak/output ratio is just 4.038, which the LTC1967
has enough margin to handle without error.
For crest factors less than 3.5, the selection of C
AVE
 as
previously described should be sufficient to avoid this
droop and modulator saturation effect. But with crest
factors above 3.5, the droop should also be checked for
each design.
Error Analyses
Once the RMS-to-DC conversion circuit is working, it is
time to take a step back and do an analysis of the accuracy
of that conversion. The LTC1967 specifications include
three basic static error terms, V
OOS
, V
IOS
 and GAIN. The
output offset is an error that simply adds to (or subtracts
APPLICATIO S I FOR ATIO
U
U
U
from) the voltage at the output. The conversion gain of the
LTC1967 is nominally 1.000 V
DCOUT
/V
RMSIN
 and the gain
error reflects the extent to which this conversion gain is
not perfectly unity. Both of these affect the results in a
fairly obvious way.
Input offset on the other hand, despite its conceptual
simplicity, effects the output in a nonobvious way. As its
name implies, it is a constant error voltage that adds
directly with the input. And it is the sum of the input and
V
IOS
 that is RMS converted.
This means that the effect of V
IOS
 is warped by the
nonlinear RMS conversion. With 0.2mV (typ) V
IOS
, and a
200mV
RMS
 AC input, the RMS calculation will add the DC
and AC terms in an RMS fashion and the effect is
negligible:
V
OUT
= (200mV AC)
2
 + (0.2mV DC)
2
= 200.0001mV
= 200mV + 1/2ppm
But with 10?less AC input, the error caused by V
IOS
 is
100?larger:
V
OUT
= (20mV AC)
2
 + (0.2mV DC)
2
= 20.001mV
= 20mV + 50ppm
This phenomena, although small, is one source of the
LTC1967s residual nonlinearity.
On the other hand, if the input is DC coupled, the input
offset voltage adds directly. With +200mV and a +0.2mV
V
IOS
, a 200.2mV output will result, an error of 0.1% or
1000ppm. With DC inputs, the error caused by V
IOS
 can be
positive or negative depending if the two have the same or
opposing polarity.
The total conversion error with a sine wave input using the
typical values of the LTC1967 static errors is computed as
follows:
V
OUT
  = ((500mV AC)
2
 + (0.2mV DC)
2
) " 1.001 + 0.1mV
= 500.600mV
= 500mV + 0.120%
V
OUT
  = ((50mV AC)
2
 + (0.2mV DC)
2
) " 1.001 + 0.1mV
= 50.150mV
= 50mV + 0.301%
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