參數(shù)資料
型號(hào)： LTC1696
廠商： Linear Technology Corporation
英文描述： Synchronous Dual Mode Phase Modulated Full Bridge Controllers
中文描述： 同步相位調(diào)制的雙模式全橋控制器
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 319K
代理商： LTC1696
LTC3722-1/LTC3722-2
7
372212i
nous rectifier driver outputs (OUTE and OUTF). The nomi-
nal voltage on SPRG is 2V.
V
REF
(Pin 14/Pin 14):
Output of the 5V Reference. V
REF
is
capable of supplying up to 19mA to external circuitry. V
REF
should be decoupled to GND with a 1
μ
F ceramic capacitor.
OUTF (Pin 15/Pin 15):
50mA Driver for Synchronous
Rectifier Associated with OUTB and OUTC.
OUTE (Pin 16/Pin 16):
50mA Driver for Synchronous
Rectifier Associated with OUTA and OUTD.
OUTD (Pin 17/Pin 17):
50mA driver for Low Side of the Full
Bridge Active Leg.
V
CC
(Pin 18/Pin 18):
Supply Voltage Input to the
LTC3722-1/LTC3722-2 and 10.25V Shunt Regulator. The
chip is enabled after V
CC
has risen high enough to allow the
V
CC
shunt regulator to conduct current and the UVLO
comparator threshold is exceeded. Once the V
CC
shunt
regulator has turned on, V
CC
can drop to as low as 6V and
maintain operation.
OUTC (Pin 19/Pin 19):
50mA Driver for High Side of the
Full Bridge Active Leg.
OUTB (Pin 20/Pin 20):
50mA Driver for Low Side of the
Full Bridge Passive Leg.
OUTA (Pin 21/Pin 21):
50mA Driver for High Side of the
Full Bridge Passive Leg.
PGND (Pin 22/Pin 22):
Power Ground for the LTC3722.
The output drivers of the LTC3722 are referenced to
PGND. Connect the ceramic V
CC
bypass capacitor directly
to PGND.
GND (Pin 23/Pin 23):
All circuits other than the output
drivers in the LTC3722 are referenced to GND. Use of a
ground plane is recommended but not absolutely neces-
sary.
C
T
(Pin 24/Pin 24):
Timing Capacitor for the Oscillator.
Use a
±
5% or better low ESR ceramic capacitor for best
results.
PIU
(LTC3722-1/LTC3722-2)
recommended. The LTC3722-2 has a fixed blanking time
of approximately 80ns.
FB (Pin 6/Pin 6):
Error Amplifier Inverting Input. This is the
voltage feedback input for the LTC3722. The nominal
regulation voltage at FB is 1.204V.
SS (Pin 7/Pin 7):
Soft-Start/Restart Delay Circuitry Timing
Capacitor. A capacitor from SS to GND provides a con-
trolled ramp of the current command (LTC3722-1), or
duty cycle (LTC3722-2). During overload conditions SS is
discharged to ground initiating a soft-start cycle.
NC (Pin 8/Pin 8):
No Connection. Tie this pin to GND.
PDLY (Pin 9/Pin 9):
Passive Leg Delay Circuit Input. PDLY
is connected through a voltage divider to the left leg of the
bridge in adaptive ZVS mode. In fixed ZVS mode, a voltage
between 0V and 2.5V on PDLY, programs a fixed ZVS
delay time for the passive leg transition.
SBUS (Pin 10/Pin 10):
Line Voltage Sense Input. SBUS is
connected to the main DC voltage feed by a resistive
voltage divider when using adaptive ZVS control. The
voltage divider is designed to produce 1.5V on SBUS at
nominal V
IN
. If SBUS is tied to V
REF
, the LTC3722-1/
LTC3722-2 is configured for fixed mode ZVS control.
ADLY (Pin 11/Pin 11):
Active Leg Delay Circuit Input.
ADLY is connected through a voltage divider to the right
leg of the bridge in adaptive ZVS mode. In fixed ZVS mode,
a voltage between 0V and 2.5V on ADLY, programs a fixed
ZVS delay time for the active leg transition.
UVLO (Pin 12/Pin 12):
Input to Program System Turn-On
and Turn-Off Voltages. The nominal threshold of the UVLO
comparator is 5V. UVLO is connected to the main DC
system feed through a resistor divider. When the UVLO
threshold is exceeded, the LTC3722-1/LTC3722-2 com-
mences a soft start cycle and a 10
μ
A (nominal) current is
fed out of UVLO to program the desired amount of system
hysteresis. The hysteresis level can be adjusted by chang-
ing the resistance of the divider.
SPRG (Pin 13/Pin 13):
A Resistor is connected between
SPRG and GND to set the turn-off delay for the synchro-
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