參數(shù)資料
型號(hào): LTC1696
廠商: Linear Technology Corporation
英文描述: Synchronous Dual Mode Phase Modulated Full Bridge Controllers
中文描述: 同步相位調(diào)制的雙模式全橋控制器
文件頁數(shù): 15/28頁
文件大小: 319K
代理商: LTC1696
LTC3722-1/LTC3722-2
15
372212i
Powering the LTC3722-1/LTC3722-2
The LTC3722-1/LTC3722-2 utilize an integrated V
CC
shunt
regulator to serve the dual purposes of limiting the voltage
applied to V
CC
as well as signaling that the chip’s bias
voltage is sufficient to begin switching operation (under
voltage lockout). With its typical 10.2V turn-on voltage
and 4.2V UVLO hysteresis, the LTC3722-1/LTC3722-2 is
tolerant of loosely regulated input sources such as an
auxiliary transformer winding. The V
CC
shunt is capable of
sinking up to 25mA of externally applied current. The
UVLO turn-on and turn-off thresholds are derived from an
internally trimmed reference making them extremely ac-
curate. In addition, the LTC3722-1/LTC3722-2 exhibits
very low (145
μ
A typ) start-up current that allows the use
of 1/8W to 1/4W trickle charge start-up resistors.
The trickle charge resistor should be selected as follows:
R
START(MAX)
= V
IN(MIN)
– 10.7V/250
μ
A
Adding a small safety margin and choosing standard
values yields:
APPLICATION
DC/DC
Off-Line
PFC Preregulator
V
IN
RANGE
36V to 72V
85V to 270V
RMS
390V
DC
R
START
100k
430k
1.4M
Fixed Delay Mode
The LTC3722-1/LTC3722-2 provides the flexibility through
the SBUS pin to disable the DirectSense delay circuitry and
enable fixed ZVS delays. The level of fixed ZVS delay is
proportional to the voltage programmed through the volt-
age divider on the PDLY and ADLY pins. See Figure3 for
more detail.
Programming Adaptive Delay Time-Out
The LTC3722-1/LTC3722-2 controllers include a feature
to program the maximum time delay before a bridge
switch turn on command is summoned. This function will
come into play if there is not enough energy to commutate
a bridge leg to the opposite supply rail, therefore bypass-
ing the adaptive delay circuitry. The time delay can be set
with an external resistor connected between DPRG and
V
REF
( see Figure 4). The nominal regulated voltage on
DPRG is 2V. The external resistor programs a current
which flows into DPRG. The delay can be adjusted from
approximately 35ns to 300ns, depending on the resistor
value. If DPRG is left open, the delay time is approximately
400ns. The amount of delay can also be modulated based
on an external current source that feeds current into
DPRG. Care must be taken to limit the current fed into
DPRG to 350
μ
A or less.
Figure 3. Setup for Fixed ZVS Delays
ADLY
PDLY
V
REF
SBUS
3722 F03
R1
R2
R3
Figure 5. Bias Configurations
3722 F04
12V
±
10%
1.5k
V
CC
V
IN
V
CC
C
HOLD
1N5226
3V
0.1
μ
F
0.1
μ
F
V
BIAS
< V
UVLO
R
START
1N914
+
Figure 4. Delay Timeout Circuitry
+
TURN-ON
OUTPUT
SBUS
+
V
2V
V
REF
DPRG
R
DPRG
3722 F04
OPERATIOU
V
CC
should be bypassed with a 0.1
μ
F to 1
μ
F multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the V
CC
supply before the
bootstrap winding, or an auxiliary regulator circuit takes
over.
C
HOLDUP
= (I
CC
+ I
DRIVE
) t
DELAY
/3.8V
(minimum UVLO hysteresis)
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3722-1/LTC3722-2. Refer to
Figure 5 for various bias supply configurations.
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