參數(shù)資料
型號(hào)： LTC1696
廠商： Linear Technology Corporation
英文描述： Synchronous Dual Mode Phase Modulated Full Bridge Controllers
中文描述： 同步相位調(diào)制的雙模式全橋控制器
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 319K
代理商： LTC1696
LTC3722-1/LTC3722-2
17
372212i
oscillator circuitry produces a 2.2V peak-to-peak ampli-
tude ramp waveform on C
T
and a narrow pulse on SYNC
that can be used to synchronize other PWM chips. Typical
maximum duty cycles of 98.5% are obtained at 300kHz
and 96% at 1MHz. A compensating slope current is
derived from the oscillator ramp waveform and sourced
out of CS.
The desired amount of slope compensation is selected
with single external resistor. A capacitor to GND on C
T
programs the switching frequency. The C
T
ramp dis-
charge current is internally set to a high value (>10mA).
The dedicated SYNC I/O pin easily achieves synchroniza-
tion. The LTC3722-1/LTC3722-2 can be set up to either
synchronize other PWM chips or be synchronized by
another chip or external clock source. The 1.8V SYNC
threshold allows the LTC3722-1/LTC3722-2 to be syn-
chronized directly from all standard 3V and 5V logic
families.
Design Procedure:
1. Choose C
T
for the desired oscillator frequency. The
switching frequency selected must be consistent with the
power magnetics and output power level. This is detailed
in the Transformer Design section. In general, increasing
the switching frequency will decrease the maximum achiev-
able output power, due to limitations of maximum duty
cycle imposed by transformer core reset and ZVS. Re-
member that the output frequency is 1/2 that of the
oscillator.
C
T
= 1/(13.4k f
OSC
)
Example: Desired f
OSC
= 330kHz
C
T
= 1/(13.4k f
OSC
) = 226pF, choose closest standard
value of 220pF. A 5% or better tolerance multilayer NPO
or X7R ceramic capacitor is recommended for best
performance.
2. The LTC3722-1/LTC3722-2 can either synchronize other
PWMs, or be synchronized to an external frequency source
or PWM chip. See Figure 8 for details.
3. Slope compensation is required for most peak current
mode controllers in order to prevent subharmonic oscilla-
Figure 8a. SYNC Output (Master Mode)
Figure 8b. SYNC Input from an External Source
LTC3722
LTC3722
LTC3722
C
T
C
T
C
T
C
T
C
T
C
T
SYNC
SYNC
SYNC
5.1k
5.1k
5.1k
1k
1k
UP TO
5 SLAVES
SLAVES
MASTER
C
OF SLAVE(S) IS
1.25 C
T
OF MASTER.
3722 F06a
LTC3722
C
T
C
T
SYNC
5.1k
1k
3722 F06b
EXTERNAL
FREQUENCY
SOURCE
AMPLITUDE > 1.8V
100ns < PW < 0.4/
tion of the current control loop. In general, if the system
duty cycle exceeds 50% in a fixed frequency, continuous
current mode converter, an unstable condition exists
within the current control loop. Any perturbation in the
current signal is amplified by the PWM modulator result-
ing in an unstable condition. Some common manifesta-
tions of this include alternate pulse nonuniformity and
pulse width jitter. Fortunately, this can be addressed by
adding a corrective slope to the current sense signal or by
subtracting the same slope from the current command
signal (error amplifier output). In theory, the current
doubler output configuration does not require slope com-
pensation since the output inductor duty cycles only
approach 50%. However, transient conditions can mo-
mentarily cause higher duty cycles and therefore, the
possibility for unstable operation. The exact amount of
required slope compensation is easily programmed by the
LTC3722-1/LTC3722-2 with the addition of a single exter-
nal resistor (see Figure 9). The LTC3722-1/LTC3722-2
generates a current that is proportional to the instanta-
neous voltage on C
T
, (33
μ
A/V
(CT)
). Thus, at the peak of C
T
,
this current is approximately 82.5
μ
A and is output from
the CS pin. A resistor connected between CS and the
external current sense resistor sums in the required amount
OPERATIOU
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