參數(shù)資料
型號(hào)： LTC1415ISW
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 12-Bit, 1.25Msps, 55mW Sampling A/D Converter
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28
封裝： 0.300 INCH, PLASTIC, SO-28
文件頁(yè)數(shù)： 15/24頁(yè)
文件大小： 481K
代理商： LTC1415ISW
15
LTC1415
APPLICATIO
S I
N
FOR
ATIO
U
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1415 has differential inputs to minimize noise
coupling. Common mode noise on the +A
IN
and –A
IN
leads will be rejected by the input CMRR. The –A
IN
input
can be used as a ground sense for the +A
IN
input; the
LTC1415 will hold and convert the difference voltage
between +A
IN
and –A
IN
. The leads to +A
IN
(Pin 1) and –A
IN
(Pin 2) should be kept as short as possible. In applications
where this is not possible, the +A
IN
and –A
IN
traces should
be run side by side to equalize coupling.
W
U
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10
μ
F bypass
capacitors should be used at the V
DD
and REFCOMP pins
as shown in the Typical Application on the fist page of this
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypass-
ing in a small board space. Alternatively 10
μ
F tantalum
capacitors in parallel with 0.1
μ
F ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of a suggested evaluation board. The layout demon-
strates the proper use of decoupling capacitors and ground
plane with a two layer printed circuit board.
LTC1415 F12
+A
IN
AGND
REFCOMP
AV
DD
DV
DD
OGND
LTC1415
DIGITAL
SYSTEM
0.1
μ
F
+
–
ANALOG
INPUT
CIRCUITRY
5
4
2
28
27
OV
DD
26
19
DGND
14
1
0.1
μ
F
10
μ
F
10
μ
F
–A
IN
+
+
ANALOG GROUND PLANE
Figure 12. Power Supply Grounding Practice
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