APPLICATION INFOR
參數資料
型號: LTC1298IS8#PBF
廠商: Linear Technology
文件頁數: 8/24頁
文件大?。?/td> 0K
描述: IC A/D CONV SAMPLING 12BIT 8SOIC
標準包裝: 100
位數: 12
采樣率(每秒): 11.1k
數據接口: MICROWIRE?,串行,SPI?
轉換器數目: 1
功率耗散(最大): 1.8mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
輸入數目和類型: 2 個單端,單極
產品目錄頁面: 1346 (CN2011-ZH PDF)
16
LTC1286/LTC1298
APPLICATION INFORMATION
WU
U
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
age on the selected “–” input must remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 12 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 12/fCLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
CLK. In most cases VERROR will not be significant. For a
60Hz signal on the “–” input to generate a 1/4LSB error
(305
V) with the converter running at CLK = 200kHz, its
peak value would have to be 13.48mV.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1286/
LTC1298 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
“+” Input Settling
The input capacitor of the LTC1286 is switched onto “+”
input during the tSMPL time (see Figure 1) and samples the
input signal within that time. However, the input capacitor
of the LTC1298 is switched onto “+” input during the
sample phase (tSMPL, see Figure 7). The sample phase is
1 1/2 CLK cycles before conversion starts. The voltage on
the “+” input must settle completely within tSMPLE for the
LTC1286 and the LTC1298 respectively. Minimizing
RSOURCE+ and C1 will improve the input settling time. If a
large “+” input source resistance must be used, the
sample time can be increased by using a slower CLK
frequency.
“–” Input Settling
At the end of the tSMPL, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 7).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settles completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing RSOURCE–
and C2 will improve settling time. If a large “–” input
source resistance must be used, the time allowed for
settling can be extended by using a slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the“+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 6
s (“+”
input) which occur at the maximum clock rate of 200kHz.
Source Resistance
The analog inputs of the LTC1286/LTC1298 look like a
20pF capacitor (CIN) in series with a 500 resistor (RON)
as shown in Figure 8. CIN gets switched between the
selected “+” and “–” inputs once during each conversion
cycle. Large external source resistors and capacitances
Figure 8. Analog Input Equivalent Circuit
RON = 500
CIN = 20pF
LTC1286/98
“+”
INPUT
RSOURCE
+
VIN +
C1
“–”
INPUT
RSOURCE
VIN
C2
LTC1286/98 F08
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