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| 型號： | AD7264BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 2CH 1MSPS 48LQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 175mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
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1 MSPS, 14-Bit, Simultaneous Sampling
SAR ADC with PGA and Four Comparators
Data Sheet
AD7264
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2008–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Dual, simultaneous sampling, 14-bit, 2-channel ADC
True differential analog inputs
Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,
×24, ×32, ×48, ×64, ×96, ×128
Throughput rate per ADC
1 MSPS for AD7264
500 kSPS for AD7264-5
Analog input impedance: >1 GΩ
Wide input bandwidth
3 dB bandwidth: 1.7 MHz at gain = 2
4 on-chip comparators
SNR: 78 dB typical at gain = 2, 71 dB typical at gain = 32
Device offset calibration
System gain calibration
On-chip reference: 2.5 V
40°C to +105°C operation
High speed serial interface
Compatible with SPI, QSPI, MICROWIRE, and DSP
48-lead LFCSP and LQFP packages
GENERAL DESCRIPTION
The AD7264 is a dual, 14-bit, high speed, low power, successive
approximation ADC that operates from a single 5 V power supply
and features throughput rates of up to 1 MSPS per on-chip ADC
(500 kSPS for the AD7264-5). Two complete ADC functions
allow simultaneous sampling and conversion of two channels.
Each ADC is preceded by a true differential analog input with a
PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6,
×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.
The AD7264 contains four comparators. Comparator A and
Comparator B are optimized for low power, whereas Comparator C
and Comparator D have fast propagation delays. The AD7264
features a calibration function to remove any device offset error
and programmable gain adjust registers to allow for input path
(for example, sensor) offset and gain compensation. The AD7264
has an on-chip 2.5 V reference that can be disabled if an external
reference is preferred. The AD7264 is available in 48-lead LFCSP
and LQFP packages.
The AD7264 is ideally suited for monitoring small amplitude
signals from a variety of sensors. The parts include all the
functionality needed for monitoring the position feedback signals
from a variety of analog encoders used in motor control systems.
FUNCTIONAL BLOCK DIAGRAM
AGND
DGND
DOUTB
PD1
PD0/DIN
PD2
VREFA
AVCC
VA+
VA–
VB+
VB–
CB+
CB–
CA+
CA–
CD+
CD–
CC+
CC–
VREFB
CA_CBVCC
CA_CB_GND
CC_CDVCC
CC_CD_GND
COMP
COUTC
COUTB
COUTA
COUTD
DOUTA
PGA
T/H
BUF
T/H
BUF
PGA
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
REF
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
OUTPUT
DRIVERS
OUTPUT
DRIVERS
OUTPUT
DRIVERS
OUTPUT
DRIVERS
VDRIVE
G3
G2
G1
G0
CAL
CS
SCLK
REFSEL
06732-
001
AD7264
OUTPUT
DRIVERS
OUTPUT
DRIVERS
Figure 1.
PRODUCT HIGHLIGHTS
1. Integrated PGA with a variety of flexible gain settings to
allow detection and conversion of low level analog signals.
2. Each PGA is followed by a dual simultaneous sampling
ADC, featuring throughput rates of 1 MSPS per ADC
(500 kSPS for the AD7264-5). The conversion result of
both ADCs is simultaneously available on separate data
lines or in succession on one data line if only one serial
port is available.
3. Four integrated comparators that can be used to count
signals from pole sensors in motor control applications.
4. Internal 2.5 V reference.
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