參數(shù)資料
型號(hào)： AD7264BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 2CH 1MSPS 48LQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 175mW
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
輸入數(shù)目和類型： *
產(chǎn)品目錄頁(yè)面： 777 (CN2011-ZH PDF)
Data Sheet
AD7264
Rev. B | Page 23 of 28
SERIAL INTERFACE
Figure 33 and Figure 34 show the detailed timing diagrams for
the serial interface on the AD7264. The serial clock provides the
conversion clock and controls the transfer of information from
the AD7264 after the conversion. The AD7264 has two output
pins corresponding to each ADC. Data can be read from the
AD7264 using both DOUTA and DOUTB. Alternatively, a single
output pin of the user’s choice can be used. The SCLK input
signal provides the clock source for the serial interface.
The falling edge of CS puts the track-and-hold into hold mode,
at which point the analog input is sampled. The conversion is
also initiated at this point and requires a minimum of 19 SCLK
cycles to complete. The DOUTx lines remain in three-state while
the conversion is taking place. On the 19th SCLK falling edge, the
AD7264 returns to track mode and the DOUTA and DOUTB lines
are enabled. The data stream consists of 14 bits of data, MSB first.
The MSB of the conversion result is clocked out on the 19th
SCLK falling edge to be read by the microcontroller or DSP on
the subsequent SCLK falling edge (the 20th falling edge). The
remaining data is then clocked out by subsequent SCLK falling
edges. Thus, the 20th falling clock edge on the serial clock has
the MSB provided and also clocks out the second data bit. The
remainder of the 14-bit result follows, with the final bit in the
data transfer being valid for reading on the 33rd falling edge.
The LSB is provided on the 32nd falling clock edge.
The AD7264-5, with its 20 MHz SCLK frequency, easily
facilitates reading on the SCLK falling edge. When using a
VDRIVE voltage of 5 V with the AD7264, the maximum specified
access time (t4) is 23 ns, which enables reading on the subse-
quent falling SCLK edge after the data has been clocked out, as
described previously. However, if a VDRIVE voltage of 3 V is used
for the AD7264 and the setup time of the microcontroller or
DSP is too large to enable reading on the falling SCLK edge, it
may be necessary to read on the SCLK rising edge. In this case,
the MSB of the conversion result is clocked out on the 19th SCLK
falling edge to be read on the 20th SCLK rising edge, as shown in
Figure 35. This is possible because the hold time (t5) is longer for
lower VDRIVE voltages. If the data access time is too long to accom-
modate the setup time of the chosen processor, an alternative to
reading on the rising SCLK edge is to use a slower SCLK frequency.
On the rising edge of CS, DOUTA and DOUTB go back into three-
state. If CS is not brought high after 33 SCLK cycles but is instead
held low for an additional 14 SCLK cycles, the data from ADC B
is output on DOUTA after the ADC A result. Likewise, the data
from ADC A is output on DOUTB after the ADC B result. This is
illustrated in Figure 34, which shows the DOUTA example. In this
case, the DOUT line in use goes back into three-state on the 47th
SCLK falling edge or the rising edge of CS, whichever occurs first.
If the falling edge of SCLK coincides with the falling edge of CS,
the falling edge of SCLK is not acknowledged by the AD7264,
and the next falling edge of SCLK is the first one registered after
the falling edge of CS.
CS
SCLK
1
5
19
DOUTA
THREE-STATE
t4
2
3
4
20
t5
THREE-
STATE
t7
t3
18
DB11A
DB12A
DB13A
21
31
32
33
DB1A
DB0A
DOUTB
THREE-STATE
THREE-
STATE
DB11B
DB12B
DB13B
DB1B
DB0B
06732-
033
t2
t9
t8
tQUIET
t6
FIRST DATA BIT CLOCKED
OUT ON THIS EDGE
FIRST DATA BIT READ
ON THIS EDGE
Figure 33. Normal Mode Operation
06732-
034
CS
32
33
31
21
20
19
18
DOUTA
THREE-STATE
THREE-
STATE
SCLK
1
2
45
46
47
DB13A
DB12A
DB1A
DB0A
DB13B
DB12B
DB1B
DB0B
t10
Figure 34. Reading Data from Both ADCs on One DOUT Line with 47 SCLK Cycles
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