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參數(shù)資料
| 型號： | LTC1298IS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV SAMPLING 12BIT 8SOIC |
| 標準包裝： | 100 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 11.1k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.8mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
| 產(chǎn)品目錄頁面： | 1346 (CN2011-ZH PDF) |
10
LTC1286/LTC1298
APPLICATION INFORMATION
WU
U
SERIAL INTERFACE
The 2-channel LTC1298 communicates with micropro-
cessors and other external circuitry via a synchronous,
half duplex, 4-wire serial interface. The single channel
LTC1286 uses a 3-wire interface (see Operating Sequence
in Figures 1 and 2).
Data Transfer
The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving systems.
The LTC1286 does not require a configuration input word
and has no DIN pin. A falling CS initiates data transfer as
shown in the LTC1286 operating sequence. After CS falls
the second CLK pulse enables DOUT. After one null bit the
A/D conversion result is output on the DOUT line. Bringing
CS high resets the LTC1286 for the next data exchange.
The LTC1298 first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half duplex operation, DIN and DOUT may be tied
together allowing transmission over just 3 wires: CS, CLK
and DATA (DIN/DOUT).
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1298 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which configures the LTC1298 and starts the
conversion. After one null bit, the result of the conversion
is output on the DOUT line. At the end of the data exchange
CS should be brought high. This resets the LTC1298 in
preparation for the next data exchange.
CLK
CS
tCYC
B11
B5
B6
B7
B8
B9
B10
B11
HI-Z
DOUT
tCONV
tDATA
HI-Z
tsuCS
NULL
BIT
B4
B3
B2
B1
POWER
DOWN
POWER DOWN
B0*
NULL
BIT
B10
B9
B8
tSMPL
(MSB)
CLK
CS
tCYC
B11*
B5
B6
B7
B8
B9
B10
B11
HI-Z
DOUT
tCONV
tDATA
HI-Z
tsuCS
NULL
BIT
LTC1286/98 F01
B4
B3
B4
B5
B6
B7
B2
B1
B0
B1
B10
B9
B8
tSMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.
tDATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
Figure 1. LTC1286 Operating Sequence
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