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參數(shù)資料
| 型號： | LT6350IMS8#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO8 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 462K |
| 代理商： | LT6350IMS8#TRPBF |
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LT6350
20
6350fb
APPLICATIONS INFORMATION
RG and RF, will always result in lower output noise at the
expense of increased distortion due to increased loading of
op amp 1. Note that op amp 1 is loaded internally by the 1k
input resistor to op amp 2, and therefore external loading
should not be much heavier than 1k to avoid degrading
distortion performance.
When using RF equal to RS (for low offsets) in the gain-
of-two conguration, wideband noise can be substantially
reduced by bypassing across RF. For lowest output noise
always bypass at the +IN2 pin with a capacitor of at least
0.1μF as seen in the Typical Application schematic on the
front page. Alternatively, for systems that can tolerate
output voltage offsets, omitting R+IN2 and RF will mini-
mize output noise at the expense of larger output offset
voltage.
Using a single pole passive RC lter network at the output
of the LT6350, as shown in Figure 6, reduces the output
noise bandwidth and thereby increases the signal-to-noise
ratio of the system. For example, in a typical system with
output signals of 8VP-P, and a signal bandwidth of 100kHz,
an RC output lter with RFILT = 100Ω and CDIFF = 6.8nF,
slightly increases the output spot noise from 8.2nV√Hz to
8.4nV√Hz, but will reduce the total integrated noise from
47μV (33MHz noise bandwidth) to 3.6μV (184kHz noise
bandwidth) and improve the SNR from 96dB to 118dB.
Keep in mind that long RC time constants in the output
lter can increase the settling time at the inputs of the
ADC; incomplete settling can cause gain errors or increase
apparent crosstalk in multiplexed systems.
OUTPUT PHASE BALANCE
The topology of the LT6350 is that of a noninverting stage
followed by an inverting stage. This topology presents
a high impedance single-ended input and provides low
impedance differential outputs. The output of the inverting
buffer, OUT2, is slightly delayed with respect to the output
of the noninverting buffer, OUT1. In the LT6350, the delay
from OUT1 to OUT2 over an input bandwidth from DC to
the differential f–3dB frequency is a nearly constant 6.8ns,
as shown in the group delay plot in the Typical Performance
Characteristics section of this data sheet. The delay is
equivalent to a small phase offset from the nominal 180°
phase of the differential outputs. The size of the phase
offset grows with frequency. The phase imbalance causes
a small frequency-dependent common mode component
to appear at the outputs. A practical measure of this effect
can be found in the balance specication, which is dened
to be the change in output common mode level caused by
the presence of an output differential signal:
Balance
≡ ((VOUTDIFF/VIN)/(VOUTCM/VIN))
The balance of the LT6350 at any frequency, f, can be
approximated from the delay, td, between outputs:
Balance (dB)
20 log((4)/(2 π f td))
The approximation is very good from low frequencies up
to frequencies where the balance approaches 20dB, about
10MHz for the LT6350. At DC, the balance is limited by
the matching of the internal resistors that set the gain in
the inverting buffer. 1% matching of the resistors limits
the balance to 52dB at DC. At frequencies near the f–3dB
point of the differential transfer function, additional phase
lag and gain rolloff also contribute to balance. See the
balance plot in the Typical Performance Characteristics
for a detailed picture of Balance vs Input Frequency.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LT6360 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:18-Bit, 1.6Msps, Pseudo-Differential Unipolar SAR |
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