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參數(shù)資料
| 型號： | LT4220IGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 259K |
| 描述： | IC CTLR HOTSWAP DUAL 16-SSOP |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內(nèi)部開關： | 無 |
| 電源電壓： | 2.7 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
7
LT4220
4220f
U
U
PI FU CTIO S
V
EE
(Pin 1): Negative Supply. The negative supply input
ranges from 2.7V to 16.5V for normal operation. I
EE
is
typically 1.6mA. An internal undervoltage lockout circuit
disables the device for inputs greater than 2.45V. A 10&,
1礔 RC bypass network from V
IN
to the V
EE
pin decouples
transients from the device.
SENSEK (Pin 2): Negative Supply Current Limit Kelvin
Sense Pin. Connect to V
IN
.
SENSE
(Pin 3): Negative Supply Current Limit Sense Pin.
A sense resistor is placed in the supply path between
SENSEK and SENSE
. The current limit circuit will regulate
the voltage across the sense resistor to
50mV (SENSEK SENSE
) when the FB
voltage is less
than 0.7V. If V
FB
goes above 0.7V, the voltage across
the sense resistor decreases linearly and stops at 15mV
when V
FB
is 0V. If current limit is not used, connect to
SENSEK.
GATE
(Pin 4): Gate Drive for the External Negative Supply
N-Channel FET. An internal 10礎 current source drives the
pin. An external capacitor connected from the GATE
pin
to V
OUT
will control the rising slope of the V
OUT
signal.
The voltage is clamped to 9V above V
EE
.
When the current limit is reached, the GATE
pin voltage
will be adjusted to maintain a constant voltage across the
R
S
resistor while the timer capacitor starts to charge. If
the TIMER pin voltage exceeds 1.24V, the fault latch will be
set and both GATE
and GATE
+
pins will be pulled low.
The GATE
pin is pulled to V
EE
whenever the ON
+
pin is
below 1.24V, the ON
pin is above 1.24V, or either supply
is in the undervoltage lockout voltage range, or the fault
latch is set by the TIMER pin rising above 1.24V.
FB
(Pin 5): Negative Power Good Comparator Input. This
pin monitors the negative output voltage (V
OUT
) with an
external resistive divider. When the voltage on FB
is
below 1.24V and the initial GATE
drive voltage has
reached a maximum (indicated by setting the internal
GATE
good latch) and the FB
+
release conditions are met,
the PWRGD pin is released. PWRGD is pulled low when the
FB
pin is above 1.185V. Note the PWRGD pin is wire-
ORed with the FB
+
pin conditions.
FB
also controls the negative supply current limit sense
amplifier input offset to provide foldback current limit. The
FB
pin linearly reduces the negative supply sense ampli-
fier offset from 52mV to 15mV for FB
in the range
0.75V < FB
< 0V. To disable V
EE
PWRGD and foldback
current limit, the FB
pin should be set to a voltage in the
range: 1.3V > FB
> V
EE
+ 0.5V but should never be more
negative then 5.8V for normal operation.
ON
(Pin 6): The Negative Supply Good Comparator Input.
This pin monitors the negative input voltage (V
EE
) with an
external resistive divider for undervoltage lockout. When
the voltage at the ON
pin is below the V
ON
H
high-to-low
threshold (1.24V), the negative supply is considered
good. If the ON
pin rises above 1.185V, both GATE
and
GATE
+
are pulled low. If ON
is not used, the ON
pin
should be set to 1.3V > ON
> V
EE
+ 0.5V.
TRACK (Pin 7): Supply Tracking Mode Control. If the TRACK
pin is pulled high, the internal supply tracking circuit will
be enabled during start-up. The TRACK circuit monitors
the FB
+
and the FB
pins to keep their magnitude within a
small voltage range by controlling the GATE
+
and GATE
charge currents. The tracking is disabled when either FB
comparator indicates the output is good. Tracking is re-
enabled if ON
+
is pulled below 1.185V, ON
is pulled above
1.185V or either supply is below the internal undervoltage
lockout. Typically, the TRACK pin is tied to GND or to V
CC
.
If left floating, tracking is enabled.
TIMER (Pin 8): Fault Time Out Control. An external timing
capacitor at this pin programs the maximum time the part
is allowed to remain in current limit before issuing a fault
and turning off the external FETs. Additionally, for
autorestart, this pin controls the time before an autorestart
is initiated.
When the part goes into current limit, a 65礎 pull-up
current source starts to charge the timing capacitor. When
the voltage reaches V
TIMERH
(1.24V), the internal fault
latch is set, FAULT pulls low and both GATE pins are pulled
low; the pull-up current will be turned off and the capacitor
is discharged by a 3.3礎 pull-down current. When the
TIMER pin falls below 0.5V, the part is allowed to restart
if the ON
+
pin is pulsed below 1.185V, thereby resetting
internal fault latchtypically done by connecting the
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