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參數資料
| 型號： | LT4220IGN#TR |
| 廠商： | Linear Technology |
| 文件頁數： | 4/16頁 |
| 文件大?。?/td> | 259K |
| 描述： | IC CTLR HOTSWAP DUAL 16-SSOP |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 2.7 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
4
LT4220
4220f
The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25?/SPAN>C. V
CC
= 5V, V
EE
= 5V, unless otherwise noted.
AC ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
W
SUPPLY VOLTAGE (V)
0
2
3
20
4220 G01
1
0
5
10
15
4
FB
+
VOLTAGE (V)
1.5
50
40
30
20
10
0
1.0 0.5
0
0.5
4220 G02
1.0 1.5
1.5 1.0 0.5
0
0.5
1.0 1.5
FB
VOLTAGE (V)
60
50
40
30
20
10
0
4220 G03
T
A
= 25癈
I
CC
I
EE
V
CC
= 5V
V
EE
= 5V
ON
+
= 2V
ON
= 2V
T
A
= 25癈
V
CC
= 5V
V
EE
= 5V
ON
+
= 2V
ON
= 2V
T
A
= 25癈
Positive Circuit Breaker Sense
Voltage vs FB
+
Voltage
Negative Circuit Breaker Sense
Voltage vs FB
Voltage
Supply Current vs Supply Voltage
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
PHLON
+
ON
+
Low to GATE
+
Low
5k Pull-Up to GATE
+
, 1nF Load Capacitor
q
0.6
0.8
1.2
祍
t
PLHON
+
ON
+
High to GATE
+
High
5k Pull-Up to GATE
+
, 1nF Load Capacitor
q
0.6
1.5
3
祍
t
PHLFB
+
FB
+
Low to PWRGD Low
5k Pull-Up to PWRGD
q
0.5
0.8
1.2
祍
t
PLHFB
+
FB
+
High to PWRGD High
5k Pull-Up to PWRGD
q
0.6
1.25
3
祍
t
PHLON
ON
Low to GATE
Low
5k Pull-Up to GATE
, 1nF Load Capacitor
q
0.6
1
1.5
祍
t
PLHON
ON
High to GATE
High
5k Pull-Up to GATE
, 1nF Load Capacitor
q
1
2.1
3.5
祍
t
PHLFB
FB
Low to PWRGD Low
5k Pull-Up to PWRGD
q
0.6
1
1.5
祍
t
PLHFB
FB
High to PWRGD High
5k Pull-Up to PWRGD
q
0.8
1.25
2
祍
t
SENSE
+
SENSE
+
to GATE
+
Low
1nF On GATE
+
, 100mV Step, 5k Pull-Up
q
1
4
6
祍
t
SENSE
SENSE
to GATE
Low
1nF On GATE
, 100mV Step, 5k Pull-Up
q
1
4
6
祍
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages referenced to ground (GND) unless
specified.
Note 3: The absolute voltage difference between FB
+
and FB
required to
force either the GATE
+
or GATE
current to 0礎.
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