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參數(shù)資料
| 型號： | LT4220IGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 259K |
| 描述： | IC CTLR HOTSWAP DUAL 16-SSOP |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 2.7 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
13
LT4220
4220f
APPLICATIO S I FOR ATIO
U
U
U
Current Limit/Electronic Circuit Breaker
The LT4220 features foldback current limit with an elec-
tronic circuit breaker that protects against short-circuits
or excessive supply currents. The current limit is set by
placing sense resistors between V
CC
(Pin 16) and SENSE
+
(Pin 15) and between SENSEK (Pin 2) and SENSE
(Pin 3).
An adjustable timer will trip an electronic circuit breaker if
the part remains in current limit for too long.
To prevent excessive power dissipation in the pass tran-
sistors and to prevent voltage spikes on the input supply
during overcurrent conditions at the output, the current
folds back as a function of the output voltage, which is
sensed at the feedback pins FB
+
and FB
. When the voltage
at the FB
+
(or FB
) pin is 0V, the sense amplifier offset is
15mV (15mV), and limits the current to I
LIMIT
= 15mV/
R
S
+
(15mV/R
S
). As the output voltage increases, the
sense amplifier offset increases until the FB
+
(or FB
)
voltage reaches 0.85V (0.75V), At which point the cur-
rent limit reaches a maximum of I
LIMIT
= 48mV/R
S
+
(52mV/R
S
).
Timer Function and Autorestart
The TIMER pin (Pin 8) provides a method for setting the
maximum time the LT4220 is allowed to operate in current
limit. When the current limit circuitry is not active, the
TIMER pin is pulled to GND by a 3.3礎 current sink.
Whenever the current limit circuit becomes active, by
either a positive or negative sense amplifier operating in
current limit, a 65礎 pull-up current source is connected
to the TIMER pin and the voltage rises with a slope equal
to dV/dt = 65礎/C
TIMER
. The desired current limit time (t)
can be set with a capacitor value of:
C
TIMER
= t " 65礎/1.24V
(4)
If the current limit circuit turns off, the TIMER pin will be
discharged to GND at a rate of:
dV/dt = 3.3礎/C
TIMER
(5)
Whenever the TIMER pin ramps up and reaches the 1.24V
threshold, the internal fault latch is set and the FAULT pin
(Pin 11) is pulled low. GATE
+
is pulled down to ground,
GATE
is pulled down to V
EE
, and the TIMER pin starts
ramping back to GND by the 3.3礎 current sink. After the
fault latch is set, the LT4220 can be restarted by pulling the
ON
+
pin low after the TIMER pin falls below 0.5V. The
LT4220 can also be restarted by cycling either supply
beyond its UVLO. Otherwise the part remains latched off.
For autorestart, the FAULT pin can be tied to the ON
+
pin.
The autorestart will occur after the TIMER pin falls below
0.5V.
Undervoltage Detection
The ON
+
and ON
pins can be used to detect an undervoltage
condition at the power supply inputs. The ON
+
and ON
pins are connected to analog comparators with 50mV of
hysteresis. If the ON
+
pin falls below its threshold voltage
or the ON
pin rises above its threshold voltage, the GATE
pins are pulled low and held low until the ON
+
and ON
pins
exceed their turn-on thresholds (1.24V and 1.24V). Ex-
ternal capacitance at the ON pins may be required to filter
supply ringing from crossing the ON comparator thresh-
old.
Additionally there is an internal undervoltage lockout on
both supplies of approximately V
CC
< 2.45V and V
EE
>
2.45V. If either supply is in UVLO, both GATE pins will be
pulled low and all internal latches will be reset.
ON
Protection
If the ON
pin is driven directly and not connected to the
negative supply through a resistor divider, a 10k resistor
must be connected between the driver and the ON
pin.
Power Good Detection
The LT4220 includes two comparators for monitoring the
output voltages. The FB
+
and the FB
pins are compared
against 1.24V and 1.24V internal references respectively.
The comparators exhibit 50mV of hysteresis. The com-
parator outputs are wire-ORed to the open collector PWRGD
pin that is enabled once both GATE
+
and GATE
pins have
reached their maximum gate drive voltage as indicated by
the internal gate good latches. The PWRGD pin goes high
impedance when both FB
+
and FB
inputs exceed V
FB
+
H
and V
FB
H
thresholds, GATE
+
is fully on and Gate
initially
has been fully on.
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