參數(shù)資料
型號(hào)： LT3500HMSE#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 21/28頁(yè)
文件大?。?/td> 322K
描述： IC REG DL BUCK/LINEAR 16-MSOP
標(biāo)準(zhǔn)包裝： 2,500
拓?fù)洌?/td> 降壓（降壓）（1），線性（LDO）（1）
功能： 任何功能
輸出數(shù)： 2
頻率 - 開(kāi)關(guān)： 500kHz ~ 2.4MHz
電壓/電流 - 輸出 1： 0.8 V ~ 38.9 V，2A
電壓/電流 - 輸出 2： 可調(diào)式，13mA
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 無(wú)
電源電壓： 3 V ~ 36 V
工作溫度： -40°C ~ 150°C
安裝類型： 表面貼裝
封裝/外殼： 16-TFSOP（0.118"，3.00mm 寬）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 16-MSOP，裸露焊盤(pán)
包裝： 帶卷 (TR)
LT3500
21
3500fc
APPLICATIONS INFORMATION
The PG pin has a sink capability of 400糀 when the FB and
LFB pins are below the threshold and can withstand 40V
when the outputs are in regulation. The PG pin is typically
connected to the output with a resistor and is used as an
error  ag. The resistor value should be chosen to allow the
PG voltage to drop below 0.4V in an error condition.
Example:
  V
OUT1
 = 5V, PGSINK
(MIN)
 = 200糀
  R
PG
 = (5  0.4)/200糀 = 23k?/DIV>
The PG pin has a sink capability of 800糀 when the FB
and LFB pins are above the threshold and can withstand
40V when the outputs are not in regulation. The PG pin is
typically used as a drive signal for an output disconnect
device. The PG pull-up resistor should be sized in the
same manner as the PG pull-up resistor.
Linear Regulator
The LT3500 contains an error ampli er and a NPN output
device which can be con gured as a linear regulator or as
a linear regulator controller.
With the LFB and LDRV pins con gured as shown in
Figure 1, the LDRV pin outputs a regulated voltage with a
typical current limit of 13mA.
The LDRV voltage is programmed with a resistor divider
between the output and the LFB pin. Choose the 1% resis-
tors according to:
 
 
R3=R4
V
LDRV
0.8V
1
R4 should be 10.0k or less to avoid bias current errors.
Reference designators refer to the Block Diagram in
Figure 1.
The reference voltage for the linear regulator (LFB pin)
will track the SS pin in the same manner as the FB pin of
the switching regulator.
At power-up, a reset signal sets the soft-start latch and
discharges the SS pin to approximately 0V to ensure
proper start-up. When the SS pin is fully discharged the
latch is reset and the internal 2.75糀 current source starts
to charge the SS pin.
When the SS pin voltage is below 100mV, the V
C
 pin is
pulled low which disables switching. As the SS pin voltage
rises above 100mV, the V
C
 pin is released and the outputs
are regulated to the SS voltage. When the SS pin voltage
minus 100mV exceeds the internal 0.8V reference, the
outputs are regulated to the reference. The SS pin voltage
will continue to rise until it is clamped at 2V.
In the event of a V
IN
 undervoltage lockout, the SHDN pin
driven below 0.8V, or the internal die temperature exceeding
its maximum rating during normal operation, the soft-start
latch is set, triggering a start-up sequence.
In addition, if the load exceeds the maximum output switch
current (switching regulator only), the output will start to
drop causing the V
C
 pin clamp to be activated. As long as
the V
C
 pin is clamped, the SS pin will be discharged. As
a result, the output will be regulated to the highest volt-
age that the maximum output current can support. For
example, if a 6V output is loaded by 1?the SS pin will
drop to 0.5V, regulating the output at 3V (typical current
limit time load, 3A " 1?. Once the overload condition is
removed, the output will soft-start from the temporary
voltage level to the normal regulation point.
Since the SS pin is clamped at 2V and has to discharge to
0.9V before taking control of regulation, momentary over-
load conditions will be tolerated without a soft-start recov-
ery. The typical time before the SS pin takes control is:
 
 
t
SS(CONTROL)
=
C
SS
"1.1V
600糀
Power Good Indicators
The PG and PG pins are collector outputs of an internal
comparator. The comparator compares the voltages of
the FB and LFB pins to 90% of the reference voltage with
30mV of hysterisis.
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