參數(shù)資料
型號(hào)： LT3500HMSE#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 322K
描述： IC REG DL BUCK/LINEAR 16-MSOP
標(biāo)準(zhǔn)包裝： 2,500
拓?fù)洌?/td> 降壓（降壓）（1），線性（LDO）（1）
功能： 任何功能
輸出數(shù)： 2
頻率 - 開(kāi)關(guān)： 500kHz ~ 2.4MHz
電壓/電流 - 輸出 1： 0.8 V ~ 38.9 V，2A
電壓/電流 - 輸出 2： 可調(diào)式，13mA
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 無(wú)
電源電壓： 3 V ~ 36 V
工作溫度： -40°C ~ 150°C
安裝類型： 表面貼裝
封裝/外殼： 16-TFSOP（0.118"，3.00mm 寬）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 16-MSOP，裸露焊盤(pán)
包裝： 帶卷 (TR)
LT3500
10
3500fc
OPERATION
The LT3500 is a constant frequency, current mode buck
converter with an internal 2.3A switch plus a linear regula-
tor with 13mA output capability. Control of both outputs
is achieved with a common SHDN pin, internal regulator,
oscillator, undervoltage detect, soft-start, thermal shut-
down and power-on reset.
If the SHDN pin is taken below its 0.8V threshold, the
LT3500 will be placed in a low quiescent current mode.
In this mode the LT3500 typically draws 12糀 from the
V
IN
 pin.
When the SHDN pin is  oated or driven above 0.76V, the
internal bias circuits turn on generating an internal regu-
lated voltage, 0.8(V
FB
) and 1V(R
T
/SYNC) references, and
a POR signal which sets the soft-start latch.
As the R
T
/SYNC pin reaches its 1V regulation point, the
internal oscillator will start generating a clock signal at a
frequency determined by the resistor from the R
T
/SYNC
pin to ground. Alternatively, if a synchronization signal is
detected by the LT3500 at the R
T
/SYNC pin, a clock signal
will be generated at the incoming frequency on the rising
edge of the synchronization pulse. In addition, the internal
slope compensation will be automatically adjusted to pre-
vent subharmonic oscillation during synchronization.
The LT3500 is a constant frequency, current mode step-
down converter. Current mode regulators are controlled
by an internal clock and two feedback loops that control
the duty cycle of the power switch. In addition to the
normal error ampli er, there is a current sense ampli er
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error ampli er commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180?shift will occur. The current fed system
will have 90?phase shift at a much lower frequency, but
will not have the additional 90?shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
During power up, the POR signal sets the soft-start latch,
which discharges the SS pin to ensure proper start-up
operation. When the SS pin voltage drops below 100mV,
the V
C
 pin is driven low disabling switching and the soft-
start latch is reset. Once the latch is reset the soft-start
capacitor starts to charge with a typical value of 2.75糀.
As the voltage rises above 100mV on the SS pin, the V
C
 
pin will be driven high by the error ampli er. When the
voltage on the V
C
 pin exceeds 0.8V, the clock set-pulse sets
the driver  ip- op which turns on the internal power NPN
switch. This causes current from V
IN
, through the NPN
switch, inductor and internal sense resistor, to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
V
C
 pin, the  ip- op is reset and the internal NPN switch
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceeds the predetermined level at the start of a clock cycle,
the  ip- op will not be set resulting in a further decrease in
inductor current. Since the output current is controlled by
the V
C
 voltage, output regulation is achieved by the error
ampli er continually adjusting the V
C
 pin voltage.
The error ampli er is a transconductance ampli er that
compares the FB voltage to either the SS pin voltage minus
100mV or an internally regulated 800mV, whichever is
lowest. Compensation of the loop is easily achieved with
a simple capacitor or series resistor/capacitor from the
V
C
 pin to ground.
Since the SS pin is driven by a constant current source, a
single capacitor on the soft-start pin will generate controlled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
mum current dictated by the V
C
 pin clamp, the SS pin
will be discharged, lowering the regulation point until the
output voltage can be supported by the maximum current.
When overload is removed, the output will soft-start from
the overload regulation point.
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