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參數(shù)資料
| 型號(hào)： | LT3150CGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大?。?/td> | 259K |
| 描述： | IC REG CTRLR SGL POS ADJ 16-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | More Information on LDOs |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 正，可調(diào)式 |
| 輸出數(shù)： | 1 |
| 輸出電壓： | 2.5 V ~ 18.4 V |
| 電流 - 電源： | 12mA |
| 輸入電壓： | 1.5 V ~ 10 V，10 V ~ 20 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
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3
LT3150
3150f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
A
VOL
Large-Signal Voltage Gain
V
GATE
= 3V to 10V
q
69
84
dB
V
OL
GATE Output Swing Low (Note 4)
I
GATE
= 0mA
q
2.5
3
V
V
OH
GATE Output Swing High
I
GATE
= 0mA
q
V
IN2
1.6 V
IN2
1
V
I
POS
+ I
NEG
Supply Current
3V d I
POS
d 20V
q
0.3
0.625
1
mA
Current Limit Threshold Voltage
42
50
58
mV
q
37
50
63
mV
Current Limit Threshold Voltage
3V d I
POS
d 20V
q
0.20
0.50
%/V
Line Regulation
SHDN2 Sink Current
Current Flows Into Pin
q
2.5
5.0
8.0
礎(chǔ)
SHDN2 Source Current
Current Flows Out of Pin
q
8
15
23
礎(chǔ)
SHDN2 Low Clamp Voltage
q
0.1
0.25
V
SHDN2 High Clamp Voltage
q
1.50
1.85
2.20
V
SHDN2 Threshold Voltage
q
1.18
1.21
1.240
V
SHDN2 Threshold Hysteresis
q
50
100
150
mV
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
T
J
= T
A
+ (P
D
" 130癈/W)
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25?/SPAN>C.
V
IN1
= 1.5V, V
SHDN1
= V
IN1
, V
IN2
= 12V, GATE = 6V, I
POS
= I
NEG
= 5V, V
SHDN2
= 0.75V unless otherwise noted.
Note 3: Switch current limit is guaranteed by design and/or correlation to
static test.
Note 4: The V
GS(th)
of the external MOSFET must be greater than
3V V
OUT
.
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