參數(shù)資料
型號(hào)： LT3150CGN#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 11/20頁(yè)
文件大小： 259K
描述： IC REG CTRLR SGL POS ADJ 16-SSOP
產(chǎn)品培訓(xùn)模塊： More Information on LDOs
標(biāo)準(zhǔn)包裝： 2,500
類型： 正，可調(diào)式
輸出數(shù)： 1
輸出電壓： 2.5 V ~ 18.4 V
電流 - 電源： 12mA
輸入電壓： 1.5 V ~ 10 V，10 V ~ 20 V
工作溫度： 0°C ~ 70°C
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
11
LT3150
3150f
APPLICATIO S I FOR ATIO
U
U
U
solutions for microprocessor power supplies. This signifi-
cant performance benefit is what permits the elimination
of all bulk output capacitance.
Several other unique features are included in the design
that increase its functionality and robustness. These func-
tions comprise the remainder of the Block Diagram.
A high side sense, current limit amplifier provides active
current limiting for the regulator. The current limit ampli-
fier uses an external low value shunt resistor connected in
series with the external MOSFETs drain. This resistor can
be a discrete shunt resistor or can be manufactured from
a Kelvin-sensed section of free PC board trace. All load
current flows through the MOSFET drain and thus, through
the sense resistor. The advantage of using high side
current sensing in this topology is that the MOSFETs gain
and the main feedback loops gain remain unaffected. The
sense resistor develops a voltage equal to I
OUT
(R
SENSE
).
The current limit amplifiers 50mV threshold voltage is a
good compromise between power dissipation in the sense
resistor, dropout voltage impact and noise immunity.
Current limit activates when the sense resistor voltage
equals the 50mV threshold.
Two events occur when current limit activates: the first is
that the current limit amplifier drives Q5 in the Block
Diagram and clamps the positive swing of the COMP node
in the main error amplifier to a voltage that provides an
output load current of 50mV/R
SENSE
. This action contin-
ues as long as the output current overload persists. The
second event is that a timer circuit activates at the SHDN2
pin. This pin is normally held low by a 5礎(chǔ) active pull-down
that limits to H 100mV above ground. When current limit
activates, the 5礎(chǔ) pull-down turns off and a 15礎(chǔ) pull-up
current source turns on. Placing a capacitor in series with
the SHDN2 pin to ground generates a programmable time
ramp voltage.
The SHDN2 pin is also the positive input of COMP1. The
negative input is tied to the internal 1.21V reference.
When the SHDN2 pin ramps above V
REF
, the comparator
drives Q7 and Q8. This action pulls the COMP and GATE
pins low and latches the external MOSFET drive off. This
condition reduces the MOSFET power dissipation to zero.
The time period until the latched-off condition occurs is
typically equal to C
SHDN2
(1.11V)/15礎(chǔ). For example, a
1礔 capacitor on the SHDN2 pin yields a 74ms ramp time.
In short, this unique circuit block performs a current limit
time-out function that latches off the regulator drive after
a predefined time period. The time-out period selected is
a function of system requirements including start-up and
safe operating area. The SHDN2 pin is internally clamped
to typically 1.85V by Q9 and R10. The comparator tied to
the SHDN2 pin has 100mV of typical hysteresis to provide
noise immunity. The hysteresis is especially useful when
using the SHDN2 pin for thermal shutdown.
Restoring normal operation after the load current fault is
cleared is accomplished in two ways. One option is to
recycle the V
IN2
 LT3150 supply voltage as long as an
external bleed path for the SHDN2 pin capacitor is pro-
vided. The second option is to provide an active reset
circuit that pulls the SHDN2 pin below V
REF
. Pulling the
SHDN2 pin below V
REF
 turns off the 15礎(chǔ) pull-up current
source and reactivates the 5礎(chǔ) pull-down. If the SHDN2
pin is held below V
REF
 during a fault condition, the regu-
lator continues to operate in current limit into a short. This
action requires being able to sink 15礎(chǔ) from the SHDN2
pin at less than 1V. The 5礎(chǔ) pull-down current source and
the 15礎(chǔ) pull-up current source are designed low enough
in value so that an external resistor divider network can
drive the SHDN2 pin to provide overvoltage protection or
to provide thermal shutdown with the use of a thermistor
in the divider network. Diode-ORing these functions to-
gether is simple to accomplish and provides multiple
functionality for one pin.
If the current limit amplifier is not used, two choices
present themselves. The simplest choice is to tie the I
NEG
pin directly to the I
POS
 pin. This action defeats current limit
and provides the simplest, no frills circuit. Applications in
which the current limit amplifier is not used are where
extremely low dropout voltages must be achieved and the
50mV threshold voltage cannot be tolerated.
However, a second available choice permits a user to pro-
vide short-circuit protection with no external sensing. This
technique is activated by grounding the I
NEG
 pin. This action
disables the current limit amplifier because Schottky diode
D1 clamps the amplifiers output and prevents Q5 from
pulling down the COMP node. In addition, Schottky diode
D2 turns off pull-down transistor Q4. Q4 is normally on and
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