參數(shù)資料
型號(hào)： LT1952MPGN#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 560 kHz SWITCHING FREQ-MAX, PDSO16
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16
文件頁(yè)數(shù)： 7/28頁(yè)
文件大小： 357K
代理商： LT1952MPGN#PBF
LT1952/LT1952-1
15
19521fe
Blanking is provided in 2 phases (Figure 6): The first phase
automatically blanks during gate rise time. Gate rise times
can vary depending on MOSFET type. For this reason the
LT1952/LT1952-1 perform true ‘leading edge blanking’ by
automatically blanking OC and ISENSE comparator outputs
until OUT rises to within 0.5V of VIN or reaches its clamp
level of 13V. The second phase of blanking starts after
the leading edge of OUT has been completed. This phase
is programmable by the user with a resistor connected
from the BLANK pin to ground. Typical durations for this
portion of the blanking period are from 45ns at RBLANK
= 10k to 540ns at RBLANK = 120k. Blanking duration can
be approximated as:
Blanking (extended) = [45(RBLANK/10k)]ns
(see graph in Typical Performance Characteristics)
APPLICATIONS INFORMATION
the MOSFET. The current limit for the converter can be
programmed by:
Current limit = (107mV/RS)(NP/NS) – (1/2)(IRIPPLE)
where:
RS = sense resistor in source of primary MOSFET
IRIPPLE = p-p ripple current in the output inductor L1
NS = number of transformer secondary turns
NP = number of transformer primary turns
Programming Slope Compensation
The LT1952/LT1952-1 use a current mode architecture
to provide fast response to load transients and to ease
frequency compensation requirements. Current mode
switchingregulatorswhichoperatewithdutycyclesabove
50%andhavecontinuousinductorcurrentmustaddslope
compensation to their current sensing loop to prevent
subharmonic oscillations. (For more information on slope
compensation, see Application Note 19.) The LT1952/
LT1952-1haveprogrammableslopecompensationtoallow
a wide range of inductor values, to reduce susceptibility
to PCB generated noise and to optimize loop bandwidth.
The LT1952/LT1952-1 program slope compensation by
inserting a resistor RSLOPE in series with the ISENSE pin
(Figure 7). The LT1952/LT1952-1 generate a current at
the ISENSE pin which is linear from 0% duty cycle to the
maximum duty cycle of the OUT pin. A simple calculation
of I(ISENSE)RSLOPE gives an added ramp to the voltage
at the ISENSE pin for programmable slope compensation.
(See both graphs ‘ISENSE Pin Current vs. Duty Cycle’ and
‘ISENSE Maximum Threshold vs Duty Cycle’ in the Typical
Performance Characteristics section.)
Figure 6. Leading Edge Blank Timing
RBLANK
(MIN)
= 10k
10k < RBLANK ≤ 240k
100ns
(AUTOMATIC)
LEADING
EDGE
BLANKING
(PROGRAMMABLE)
EXTENDED
BLANKING
CURRENT
SENSE
DELAY
OUT
BLANKING
1952 F06
0
Xns X + 45ns
[X + 45(RBLANK/10k)]ns
Programming Current Limit (OC Pin)
TheLT1952/LT1952-1useaprecise107mVsensethreshold
at the OC pin to detect overcurrent conditions in the
converter and set a soft-start latch. It is independent of
dutycyclebecauseitisnotaffectedbyslopecompensation
programmed at the ISENSE pin. The OC pin monitors the
peak current in the primary MOSFET by sensing the
voltage across a sense resistor (RS) in the source of
Figure 7. Programming Slope Compensation
CURRENT SLOPE = 35A DC
V(ISENSE) = VS + (ISENSE RSLOPE)
ISENSE = 8A + 35DC A
DC = DUTY CYCLE
FOR SYNC OPERATION
ISENSE(SYNC) = 8A + (k 35DC)A
k = fOSC/fSYNC
1952 F07
ISENSE
OUT
LT1952/
LT1952-1
OC
RS
RSLOPE
VS
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