參數(shù)資料
型號: LSI53C895
英文描述: LSI53C895 PCI to Ultra2 SCSI I/O Processor with LVD Link Universal Transceivers technical manual v3.2 12/00
中文描述: LSI53C895 PCI到Ultra2的SCSI I / O處理器與內(nèi)徑鏈接通用收發(fā)器技術(shù)手冊v3.2版12/00
文件頁數(shù): 27/166頁
文件大?。?/td> 1330K
代理商: LSI53C895
Interrupts
2-11
When the background process starts the next pass of its infinite loop
(above), it detects the unhealthy state (as mentioned above), reinitializes
the hardware, and re-enables the interrupt.
2.8 Interrupts
This section provides information on the 8032 processor and LSI53C040
interrupts.
2.8.1 8032 Processor Interrupts
The 8032 processor has two external interrupts (INT0 and INT1), which
may be set to be level or edge triggered depending upon the setting of
the control bits in the TCON register.
IT0 = H -> interrupt on falling edge of INT0 (edge triggered)
IT0 = L -> interrupt if INT0 = LOW
(level triggered)
IT1 = H -> interrupt on falling edge of INT1 (edge triggered)
IT1 = L -> interrupt if INT1 = LOW
(level triggered)
Both of these external interrupts may be configured as inputs from any
of the LSI53C040 core interrupts.
Other interrupt sources from the 8032:
SERIAL
RX
TX
TIMER0
TIMER1
TIMER2
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