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參數(shù)資料
| 型號(hào)： | LSI53C810AE |
| 英文描述： | LSI53C810AE single-chip PCI-SCSI controller |
| 中文描述： | LSI53C810AE單芯片的PCI - SCSI控制器 |
| 文件頁(yè)數(shù)： | 89/166頁(yè) |
| 文件大?。?/td> | 1330K |
| 代理商： | LSI53C810AE |
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SAF-TE Module
3-41
External Interrupt 0 ISR –
If compile time options enable DMA data or
commands, this ISR clears the DMA interrupt register, otherwise null
routine.
To enable DMA data (commands), the #Define parameter
DMA_DATA_IN_ENABLED must be set to TRUE prior to compilation.
Note:
If DMA data or commands are enabled, DMA interrupts are
mapped to External Interrupt 0 and SCSI data transfers are
handled by the DMA processor instead of through direct
I/O. For more information, see the description of the
External Interrupt 1 ISR and SCSI data transfer sections.
Function Name:
ir_external0()
Return Value: None.
External Interrupt 1 ISR –
Initiation of SCSI data transfers between the
host and target result in the execution of this ISR. Depending on the
#define settings, the data transfers between the Initiator and the Target
(data memory) are performed by using DMA (see Figure 2.6 in the
LSI53C040 Enclosure Services Processor Technical Manual
) or by
software using a Programmed I/O Method (see Figure 2.7 in the
LSI53C040 Enclosure Services Processor Technical Manual
).
The ISR flow diagrams (see
Figure 3.2
and
Figure 3.3
below) validate
that the Target has been selected, the bus is not busy, and the ID bit has
been set. Failure of one or more of these conditions results in two
actions: an error message is sent to TRACER, and the ISR terminates.
Next the ISR determines the Initiator SCSI ID and checks the SCSI
control lines for a parity error. If any errors occur, the ISR sends an error
message to TRACER and terminates. The SCSI attention (ATN) control
line is then tested and these results are possible:
If high, the target switches to message phase out and checks to see
if the received byte (
rcv_byte
) is an Identify (0x80).
If
rcv_byte
is an Identify (0x80), the message is saved and the
code repeats until the ATN is low.
If
rcv_byte
is not an Identify (0x80), the received byte is checked
for the following cases:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LSI53C825AE | LSI53C825AE single-chip PCI-SCSI controller |
| LSI53C860 | LSI53C860 PCI to Ultra SCSI I/O Processor technical manual v2.1 4/01 |
| LSI53C860E | Controller Miscellaneous - Datasheet Reference |
| LSI53C875A | LSI53C875A PCI to Ultra SCSI Controller technical manual v2.0 12/00 |
| LSI53C875E | LSI53C875E PCI-single channel Ultra SCSI controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LSI53C825A/825AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LSI53C825A/825AE PCI to Ultra SCSI I/O Processor technical manual v3.1 1/01 |
| LSI53C825A-160QFP | 制造商:LSI Corporation 功能描述: |
| LSI53C825AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LSI53C825AE single-chip PCI-SCSI controller |
| LSI53C825AJ-160QFP | 制造商:LSI Corporation 功能描述: |
| LSI53C860 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LSI53C860 PCI to Ultra SCSI I/O Processor technical manual v2.1 4/01 |
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