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OSR (Output Status Register)
.
Indicates CNTR status: Accessed by
:
READ when C/D = 1, CS = 0.
Bit # 7 6 5 4 3 2 1 0
U U U 0/1 0/1 0/1 0/1 0/1
BWT. Borrow Toggle Flip-Flop. Toggles everytime CNTR underflows
generating a borrow.
CYT. Carry Toggle Flip-Flop. Toggles everytime CNTR overflows
generating a carry.
COMPT. Compare Toggle Flip-Flop. Toggles everytime CNTR equals PR
SIGN. Sign bit. Reset ( = 0) when CNTR underflows
Set ( = 1) when CNTR overflows
UP/DOWN. Count direction indicatior in quadrature mode.
Reset ( = 0) when counting down
U = Undefined
(Forced to 1 in non-quadrature mode)
OL(Output latch
).
The OL is the output port for the CNTR. The 24 bit CNTR Value at any instant can be accessed
by performing a CNTR to OL transfer and then reading the OL in 3 READ cycle sequence of Byte 0 (OL0), Byte 1 (OL1)
and Byte 2 (OL2). The address pointer for OL0/OL1/OL2 is automatically incremented with each READ cycle.
Accessed by
:
READ when C/D = 0, CS = 0.
Bit #
7 0 7 0 7 0
OL2 OL1 OL0
(BYTE 2) (BYTE 1) (BYTE 0)
Standard Sequence for Loading and Reading OL
:
3 MCR
;
Reset OL address pointer and Transfer CNTR to OL
READ OL
;
Read Byte 0 and increment address
READ OL
;
Read Byte 1 and increment address
READ OL
;
Read Byte 2 and increment address
TABLE 1 - Register Addressing Modes
D7 D6 C/D RD WR CS COMMENT
X X X X X 1 Disable Chip for READ/WRITE
0 0 1 1 0 Write to Master Control Register (MCR)
0 1 1 1 0 Write to input control register (ICR)
1 0 1 1 0 Write to output/counter control register (OCCR)
1 1 1 1 0 Write to quadrature register (QR)
X X 0 1 0 Write to preset register (PR) and increment register
address counter.
X X 0 1 0 Read output latch (OL) and increment register
address counter
X X 1 1 0 Read output status register (OSR).
X =
Don't Care
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