參數(shù)資料
型號(hào)： LRI512-C40
廠商： 意法半導(dǎo)體
元件分類(lèi)： DRAM
英文描述： EEPROM
中文描述： EEPROM的
文件頁(yè)數(shù)： 9/54頁(yè)
文件大?。?/td> 351K
代理商： LRI512-C40
9/54
LRI512
BIT REPRESENTATION AND CODING
Data bits are encoded using Manchester coding,
according to the following schemes.
For the low data rate the same subcarrier frequen-
cy or frequencies are used, in this case the num-
ber of pulses shall be multiplied by 4 and all times
will increase by this factor.
Bit Coding Using One Subcarrier
High Data Rate.
A logic 0 starts with 8 pulses of
423.75 kHz (f
C
/32) followed by an unmodulated
time of 18,88μs as shown in Figure 12.
Figure 12. Logic 0, High Data Rate
A logic 1 starts with an unmodulated time of
18.88 μs followed by 8 pulses of 423.75 kHz (f
C
/
32) as shown in Figure 13.
Figure 13. Logic 1, High Data Rate
Low Data Rate.
A logic 0 starts with 32 pulses of
423.75 kHz (f
C
/32) followed by an unmodulated
time of 75.52 μs as shown in Figure 14.
Figure 14. Logic 0, Low Data Rate
A logic 1 starts with an unmodulated time of
75.52 μs followed by 32 pulses of 423.75 kHz (f
C
/
32) as shown in Figure 15.
Figure 15. Logic 1, Low Data Rate
AI06663
37.76 μs
AI06664
37.76 μs
AI06666
149.86 μs (ISO=151.04 μs)
AI06665
149.86 μs (ISO=151.04 μs)
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