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參數(shù)資料
| 型號(hào)： | LPC47N227TQFP |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 100 Pin Super I/O with LPC Interface for Notebook Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 130/228頁(yè) |
| 文件大?。?/td> | 1269K |
| 代理商： | LPC47N227TQFP |
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The default power on SMBus address is 010110x binary, where x reflects the state defined by the A0 pin. The
A0/RESET#/THERM#/XNOR_OUT pin requires an external pullup resistor if the RESET# or THERM# functions are
used. This limits the SMBus address to 0101101 unless external circuitry is used to override the pull-up at power-up.
SMSC DS – LPC47M192
Page 130
Rev. 03/30/05
DATASHEET
7.18.2.1
The Hardware Monitor Block SMBus implementation is a subset of the SMBus interface to the host. The Hardware
Monitor Block is a
slave-only
SMBus device. The implementation in the Hardware Monitor Block is a subset of
SMBus since it only supports four protocols.
The Read Byte, Receive Byte, Write Byte and Send Byte protocols are the only valid SMBus protocols for the
Hardware Monitor Block. The part responds to other protocols as described in the Invalid Protocol Section. Reference
the System Management Bus Specification, Rev 1.1.
The SMBus interface is used to read and write the registers in the Hardware Monitor Block. The only valid registers
for a read or write protocol are the registers shown in the Registers Section.
SMBus Slave Interface
7.18.2.1.1 Bus Protocols
Typical Write Byte, Read Byte, Send Byte and Receive Byte protocols are shown below. Register accesses are
performed using 7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. The shading indicates
the Hardware Monitor Block driving data on the SDA line; otherwise host data is on the SDA line.
The slave address is the unique SMBus Interface Address for the Hardware Monitor Block that identifies it on SMBus.
The register address field is the internal address of the register to be accessed. The register data field is the data that
the host is attempting to write to the register or the contents of the register that the host is attempting to read.
Data bytes are transferred MSB first.
When using the Hardware Monitor Block SMBus Interface, a write will always consist of the SMBus Interface Address
byte, followed by the Internal Address Register byte, then the data byte. There are two cases for a read:
1. The normal read protocol consists of a write to the Hardware Monitor Block with the SMBus Interface Address
byte, followed by the Internal Address Register byte. Then restart the Serial Communication with a Read consisting of
the SMBus Interface Address byte, followed by the data byte read from the Hardware Monitor Block. This can be
accomplished by using the Read Byte protocol or by using the Send Byte protocol followed by the Receive Byte
protocol.
2. If the Internal Address Register is known to be at the desired Address, simply read the Hardware Monitor Block
with the SMBus Interface Address byte, followed by the data byte read from the Hardware Monitor Block. This
corresponds to the Receive Byte protocol.
Write Byte
The Write Byte protocol is used to write data to the registers. The data will only be written if the protocol shown in
Table 1 is performed correctly. Only one byte is transferred at time for a Write Byte protocol.
Table 57 - SMBus Write Byte Protocol
FIELD: START
SLAVE
ADDR
7
WR
ACK
REG.
ADDR
8
ACK
REG.
DATA
8
ACK
STOP
Bits:
1
1
1
1
1
1
Read Byte
The Read Byte protocol is used to read data from the registers. The data will only be read if the protocol shown in
Table 2 is performed correctly. Only one byte is transferred at time for a Read Byte protocol.
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