參數(shù)資料
型號(hào)： LPC47N227MN
英文描述： Peripheral IC
中文描述： 外圍芯片
文件頁(yè)數(shù)： 65/228頁(yè)
文件大?。?/td> 1269K
代理商： LPC47N227MN
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Note
: The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for more
information.
SMSC DS – LPC47M192
Page 65
Rev. 03/30/05
DATASHEET
REGISTER DESCRIPTION
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are
defined by the configuration registers (see “Configuration” section). The Serial Port registers are located at
sequentially increasing addresses above these base addresses. The LPC47M192 contains two serial ports, each of
which contain a register set as described below.
Table 28 – Addressing the Serial Port
DLAB*
0
0
0
X
X
X
X
X
X
X
1
1
A2
0
0
0
0
0
0
1
1
1
1
0
0
A1
0
0
0
1
1
1
0
0
1
1
0
0
A0
0
0
1
0
0
1
0
1
0
1
0
1
REGISTER NAME
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
*Note
: DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received
first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and
convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not
accessible.
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional
shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the
Transmit Buffer when the transmission of the previous byte is complete.
INTERRUPT ENABLE REGISTER (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is
possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the
appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits
the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M192. All other system
functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of
the Interrupt Enable Register are described below.
Bit 0
This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic
“1”.
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參數(shù)描述
LPC47N227-MN 制造商:Rochester Electronics LLC 功能描述:- Bulk
LPC47N227-MT 功能描述:輸入/輸出控制器接口集成電路 Notebk I/O Contrllr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
LPC47N227-MV 功能描述:輸入/輸出控制器接口集成電路 100-Pin Mobile I/O RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
LPC47N227TQFP 制造商:Microchip Technology 功能描述:I/O Controller 制造商:Rochester Electronics LLC 功能描述:NOTEBOOK I/O CONTROLLER W/ LPC INTERFACE (TQFP PACKAGE) - Bulk
LPC47N237 制造商:SMSC 制造商全稱:SMSC 功能描述:3.3v I/O Controller for Port Replicators and Docking Stations
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