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參數(shù)資料
| 型號(hào)： | LPC2939FBD208 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM9 microcontroller with CAN, LIN, and USB |
| 中文描述： | 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, SOT-459, MS-026, LQFP-208 |
| 文件頁數(shù)： | 54/99頁 |
| 文件大?。?/td> | 1945K |
| 代理商： | LPC2939FBD208 |
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LPC2939_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
54 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Configuration of the CGU0:
For every output generator generating the base clocks a
choice can be made from the primary and secondary clock generators according to
Figure 13
.
Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be
connected to either a fractional divider (FDIV0:6) or to one of the outputs of the PLL or to
LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only
LP_OSC as source.
The fractional dividers can be connected to one of the outputs of the PLL or directly to
LP_OSC/crystal Oscillator.
The PLL is connected to the crystal oscillator.
In this way every output generating the base clocks can be configured to get the required
clock. Multiple output generators can be connected to the same primary or secondary
clock source, and multiple secondary clock sources can be connected to the same PLL
output or primary clock source.
Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL
outputs itself for example - will be blocked by hardware. The control register will not be
written, the previous value will be kept, although all other fields will be written with new
data. This prevents clocks being blocked by incorrect programming.
Default Clock Sources:
Every secondary clock generator or output generator is
connected to LP_OSC at reset. In this way the device runs at a low frequency after reset.
It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as
(one of) the first step(s) in the boot code after verifying that the high-frequency clock
generator is running.
Clock Activity Detection:
Clocks that are inactive are automatically regarded as invalid,
and values of ‘CLK_SEL’ that would select those clocks are masked and not written to the
control registers. This is accomplished by adding a clock detector to every clock
Fig 13. Structure of the clock generation scheme
LP_OSC
PLL
FDIV0:6
EXTERNAL
OSCILLATOR
002aad834
clkout
clkout120
clkout240
OUTPUT
CONTROL
clock
outputs
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| LPC2939FBD208,551 | 功能描述:ARM微控制器 - MCU IC ARM9 MCU FLASH 768KB RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
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