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| 型號： | LPC2939FBD208 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM9 microcontroller with CAN, LIN, and USB |
| 中文描述： | 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, SOT-459, MS-026, LQFP-208 |
| 文件頁數(shù)： | 40/99頁 |
| 文件大?。?/td> | 1945K |
| 代理商： | LPC2939FBD208 |
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LPC2939_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
40 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Table 21.
Symbol
LIN0/1 TXD
LIN0/1 RXD
6.14.3
I
2
C-bus serial I/O controllers
The LPC2939 each contain two I
2
C-bus controllers.
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or as a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus, and it can be
controlled by more than one bus master connected to it.
The main features if the I
2
C-bus interfaces are:
I
2
C0 and I
2
C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I
2
C-bus)
and do not support powering off of individual devices connected to the same bus lines
Easy to configure as master, slave, or master/slave
Programmable clocks allow versatile rate control
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
2
C-bus can be used for test and diagnostic purposes
All I
2
C-bus controllers support multiple address recognition and a bus monitor mode
6.14.3.1
Pin description
Table 22.
Symbol
I2C SCL0/1
I2C SDA0/1
[1]
Note that the pins are not I
2
C-bus compliant open-drain pins.
6.15 Modulation and Sampling Control SubSystem (MSCSS)
The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2939 includes four
Pulse-Width Modulators (PWMs), three 10-bit successive approximation Analog-to-Digital
Converters (ADCs) and two timers.
The key features of the MSCSS are:
LIN controller pins
Pin name
TXDL0/1
RXDL0/1
Direction
OUT
IN
Description
LIN channel 0/1 transmit data output
LIN channel 0/1 receive data input
I
2
C-bus pins
[1]
Pin name
SCL0/1
SDA0/1
Direction
I/O
I/O
Description
I
2
C clock input/output
I
2
C data input/output
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