參數(shù)資料
型號： LPC2939FBD208
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝： 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, SOT-459, MS-026, LQFP-208
文件頁數(shù)： 26/99頁
文件大?。?/td> 1945K
代理商： LPC2939FBD208
LPC2939_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
26 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Table 11.
32-bit
system
address bit
field
31 to 29
Table 12.
CS[2:0]
000
001
010
011
100
101
110
111
6.9.2
Pin description
The external static-memory controller module in the LPC2939 has the following pins,
which are combined with other functions on the port pins of the LPC2939.
Table 13
shows
the external memory controller pins.
Table 13.
Symbol
EXTBUS CSx
EXTBUS BLSy
EXTBUS WE
EXTBUS OE
EXTBUS A[23:0]
EXTBUS D[31:0] D[31:0]
6.9.3
Clock description
The external Static Memory Controller is clocked by CLK_SYS_SMC, see
Section 6.7.2
.
6.9.4
External memory timing diagrams
A timing diagram for reading from external memory is shown in
Figure 5
. The relationship
between the wait state settings is indicated with arrows.
External memory bank address bit description
Symbol
Description
BA[2:0]
external static memory base address (three most significant bits);
the base address can be found in the memory map; see
Ref. 1
. This
field contains ‘010’ when addressing an external memory bank.
chip select address space for eight memory banks; see
Ref. 1
always ‘00’; other values are ‘mirrors’ of the 16 MB bank address
16 MB memory banks address space
28 to 26
25 and 24
23 to 0
CS[2:0]
-
A[23:0]
External static memory controller banks
Bank
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
External memory controller pins
Pin name
CSx
BLSy
WE
OE
A[23:0]
Direction
OUT
OUT
OUT
OUT
OUT
IN/OUT
Description
memory bank x select, x runs from 0 to 7
byte lane select input y, y runs from 0 to 3
write enable (active LOW)
output enable (active LOW)
address bus
data bus
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