參數(shù)資料
型號(hào)： LPC2929FBD144
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁(yè)數(shù)： 41/95頁(yè)
文件大?。?/td> 1855K
代理商： LPC2929FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
41 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
6.15.2
Pin description
The pins of the LPC2926/2927/2929 MSCSS associated with the three ADC modules are
described in
Section 6.15.4.2
. Pins connected to the four PWM modules are described in
Section 6.15.5.4
, pins directly connected to the MSCSS timer 1 module are described in
Section 6.15.6.1
, and pins connected to the quadrature encoder interface are described in
Section 6.15.7.1
.
6.15.3
Clock description
The MSCSS is clocked from a number of different sources:
CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge
CLK_MSCSS_APB clocks the subsystem APB bus
CLK_MSCSS_MTMR0/1 clocks the timers
CLK_MSCSS_PWM[0:3] clocks the PWMs.
Each ADC has two clock areas; a APB part clocked by CLK_MSCSS_ADCx_APB (x = 0,
1, or 2) and a control part for the analog section clocked by CLK_ADCx = 0, 1, or 2), see
Section 6.7.2
.
All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A
which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived
from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding
clocks can be switched off.
6.15.4
Analog-to-digital converter
The MSCSS in the LPC2926/2927/2929 includes three 10-bit successive-approximation
analog-to-digital converters.
The key features of the ADC interface module are:
ADC0: Eight analog inputs; time-multiplexed; measurement range up to 5.0 V.
ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to
3.3 V.
External reference-level inputs.
400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at 2-bit
resolution.
Programmable resolution from 2-bit to 10-bit.
Single analog-to-digital conversion scan mode and continuous analog-to-digital
conversion scan mode.
Optional conversion on transition on external start input, timer capture/match signal,
PWM_sync or ‘previous’ ADC.
Converted digital values are stored in a register for each channel.
Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’
compare-value indication for each channel.
Power-down mode.
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