參數(shù)資料
型號: LPC2929FBD144
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù): 19/95頁
文件大小: 1855K
代理商: LPC2929FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
19 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
[1]
This clock is always on (cannot be switched off for system safety reasons).
[2]
In the peripheral subsystem parts of the timers, watchdog timer, SPI and UART have their own clock
source. See
Section 6.13
for details.
[3]
The clock should remain activated when system wake-up on timer or UART is required.
[4]
In the Power Clock and Reset Control subsystem parts of the CGU, RGU, and PMU have their own clock
source. See
Section 6.16
for details.
Table 8.
Base clock
BASE_MSCSS_CLK
CLK_MSCSS_APB
CLK_MSCSS_MTMR0
CLK_MSCSS_MTMR1
CLK_MSCSS_PWM0
CLK_MSCSS_PWM1
CLK_MSCSS_PWM2
CLK_MSCSS_PWM3
CLK_MSCSS_ADC0_APB APB side of ADC 0
CLK_MSCSS_ADC1_APB APB side of ADC 1
CLK_MSCSS_ADC2_APB APB side of ADC 2
CLK_MSCSS_QEI
CLK_UART0
CLK_UART1
-
CLK_SPI0
CLK_SPI1
CLK_SPI2
CLK_TMR0
CLK_TMR1
CLK_TMR2
CLK_TMR3
CLK_ADC0
APB side of the MSCSS
Timer 0 in the MSCSS
Timer 1 in the MSCSS
PWM 0
PWM 1
PWM 2
PWM 3
Quadrature encoder
UART 0 interface clock
UART 1 interface clock
CGU1 input clock
SPI 0 interface clock
SPI 1 interface clock
SPI 2 interface clock
Timer 0 clock for counter part
Timer 1 clock for counter part
Timer 2 clock for counter part
Timer 3 clock for counter part
Control of ADC 0, capture
sample result
Control of ADC 1, capture
sample result
Control of ADC 2, capture
sample result
-
CGU1 input clock
BASE_UART_CLK
BASE_ICLK0_CLK
BASE_SPI_CLK
BASE_TMR_CLK
BASE_ADC_CLK
CLK_ADC1
CLK_ADC2
reserved
BASE_ICLK1_CLK
-
-
CGU1 base clock and branch clock overview
Branch clock name
Parts of the device clocked
by this branch clock
clock out pin
USB clock
USB OTG I2C clock
Remark
BASE_OUT_CLK
BASE_USB_CLK
BASE_USB_I2C_CLK
CLK_OUT_CLK
CLK_USB_CLK
CLK_USB_I2C_CLK
Table 7.
Base clock
CGU0 base clock and branch clock overview
…continued
Branch clock name
Parts of the device clocked
by this branch clock
Remark
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