參數(shù)資料
型號： LPC2388FBD144
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Single-chip 16-bit-32-bit micro; 512 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC
封裝： LPC2388FBD144<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;
文件頁數(shù)： 23/72頁
文件大?。?/td> 1469K
代理商： LPC2388FBD144
LPC2388
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 13 July 2010
23 of 72
NXP Semiconductors
LPC2388
Single-chip 16-bit/32-bit microcontroller
The LPC2388 USB interface includes a device, host, and OTG controller. Details on
typical USB interfacing solutions can be found in
Section 14.1
.
7.11.1
USB device controller
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
7.11.1.1
Features
Fully compliant with
USB 2.0 specification
(full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While the USB is in the Suspend mode, the LPC2388 can enter one of the reduced
power modes and wake up on USB activity.
Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
7.11.2
USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine, and DMA controller. The
register interface complies with the
OHCI specification
.
7.11.2.1
Features
OHCI compliant.
Two downstream ports.
Supports per-port power switching.
7.11.3
USB OTG controller
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals.
The OTG controller integrates the host controller, device controller, and a master-only
I
2
C-bus interface to implement OTG dual-role device functionality. The dedicated I
2
C-bus
interface controls an external OTG transceiver.
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