參數(shù)資料
型號： LPC2388FBD144
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Single-chip 16-bit-32-bit micro; 512 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC
封裝： LPC2388FBD144<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;
文件頁數(shù)： 22/72頁
文件大?。?/td> 1469K
代理商： LPC2388FBD144
LPC2388
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 13 July 2010
22 of 72
NXP Semiconductors
LPC2388
Single-chip 16-bit/32-bit microcontroller
via the EMC, as well as the SRAM located on another AHB, if it is not being used by the
USB block. However, using memory other than the Ethernet SRAM, especially off-chip
memory, will slow Ethernet access to memory and increase the loading of its AHB.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII
(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial
bus.
7.10.1
Features
Ethernet standards support:
–
Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
–
Fully compliant with IEEE standard 802.3.
–
Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
–
Flexible transmit and receive frame options.
–
Virtual Local Area Network (VLAN) frame support.
Memory management:
–
Independent transmit and receive buffers memory mapped to shared SRAM.
–
DMA managers with scatter/gather DMA and arrays of frame descriptors.
–
Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
–
Receive filtering.
–
Multicast and broadcast frame support for both transmit and receive.
–
Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
–
Selectable automatic transmit frame padding.
–
Over-length frame support for both transmit and receive allows any length frames.
–
Promiscuous receive mode.
–
Automatic collision back-off and frame retransmission.
–
Includes power management by clock switching.
–
Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
Physical interface:
–
Attachment of external PHY chip through standard RMII interface.
–
PHY register access is available via the MIIM interface.
7.11 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
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LPC2420_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
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