參數(shù)資料
型號(hào): LPC2378FBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Single-chip 16-bit-32-bit microcontrollers; 512 kB flash with ISP-IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC-DAC
封裝: LPC2377FBD144<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2378FBD144<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.htm
文件頁數(shù): 50/68頁
文件大?。?/td> 1443K
代理商: LPC2378FBD144
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11.5 Static external memory interface
L
A
P
R
5
N
L
S
[1]
V
OH
= 2.5 V, V
OL
= 0.2 V.
V
IH
= 2.5 V, V
IL
= 0.5 V.
T
cy(CCLK)
=
1
CCLK
.
Latest of address valid, CS LOW, OE LOW to data valid.
[2]
[3]
[4]
[5]
Earliest of CS HIGH, OE HIGH, address change to data invalid.
Table 12.
C
L
= 30 pF, T
amb
=
40
°
C to 85
°
C, V
DD(DCDC)(3V3)
= V
DD(3V3)
= 3.0 V to 3.6 V, AHB clock = 1 MHz
Symbol
Parameter
Conditions
Common to read and write cycles
[1]
t
CSLAV
CS LOW to address valid
time
Read cycle parameters
[1][2]
t
OELAV
OE LOW to address valid
time
t
CSLOEL
CS LOW to OE LOW time
t
am
memory access time
Dynamic characteristics: Static external memory interface
Min
Typ
Max
Unit
0.29
0.20
2.54
ns
0.29
0.20
2.54
ns
0.78 + T
cy(CCLK)
×
WAITOEN 0 + T
cy(CCLK)
×
WAITOEN
[3][4]
(WAITRD
WAITOEN + 1)
×
T
cy(CCLK)
8.11
[5]
0
0.49
0.20
0.49 + T
cy(CCLK)
×
WAITOEN
(WAITRD
WAITOEN + 1)
×
T
cy(CCLK)
12.70
-
0.20
2.44
ns
ns
(WAITRD
WAITOEN + 1)
×
T
cy(CCLK)
9.57
-
0
0.20
t
h(D)
t
CSHOEH
t
OEHANV
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
OE LOW to OE HIGH time
ns
ns
ns
t
OELOEH
0.59 + (WAITRD
WAITOEN + 1)
×
T
cy(CCLK)
0 + (WAITRD
WAITOEN +
1)
×
T
cy(CCLK)
0.10 + (WAITRD
WAITOEN + 1)
×
T
cy(CCLK)
Write cycle parameters
[1]
t
CSLBLSL
CS LOW to BLS LOW time
0.88 + T
cy(CCLK)
×
(1 +
WAITWEN)
0.68
0
0.10 + T
cy(CCLK)
×
(1 +
WAITWEN)
2.54
2.64
0 + T
cy(CCLK)
×
(WAITWR
WAITWEN + 1)
0.20 + T
cy(CCLK)
0.20 + T
cy(CCLK)
×
(1 +
WAITWEN)
5.86
4.79
0.10 + T
cy(CCLK)
×
(WAITWR
WAITWEN + 1)
2.74 + T
cy(CCLK)
ns
t
BLSDV
t
CSLDV
t
BLSLBLSH
BLS LOW to BLS HIGH
time
t
BLSHANV
BLS HIGH to address
invalid time
t
BLSHDNV
BLS HIGH to data invalid
time
BLS LOW to data valid time
CS LOW to data valid time
ns
ns
ns
[3]
0.78 + T
cy(CCLK)
×
(WAITWR
WAITWEN + 1)
[3]
0 + T
cy(CCLK)
ns
[3]
0.78
2.54
5.96
ns
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