參數(shù)資料
型號(hào)： LPC2378
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 16-bit/32-bit microcontrollers; 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
中文描述： 單芯片16-bit/32-bit微控制器，512的ISP /國(guó)際檢察官聯(lián)合會(huì)，以太網(wǎng)，USB 2.0，CAN和10 kB閃存位的ADC / DAC
文件頁數(shù)： 44/54頁
文件大小： 203K
代理商： LPC2378
LPC2378_1
NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 December 2006
44 of 54
NXP Semiconductors
LPC2378
Fast communication chip
Table 9.
C
L
= 25 pF T
amb
= 40
°
C.
Symbol
Parameter
Common to read and write cycles
t
CHAV
XCLK HIGH to address valid
time
t
CHCSL
XCLK HIGH to CS LOW time
t
CHCSH
XCLK HIGH to CS HIGH
time
t
CHANV
XCLK HIGH to address
invalid time
Read cycle parameters
t
CSLAV
CS LOW to address valid
time
t
OELAV
OE LOW to address valid
time
t
CSLOEL
CS LOW to OE LOW time
t
am
memory access time
External memory interface dynamic characteristics
Conditions
Min
Typ Max
Unit
-
-
10
ns
-
-
-
-
10
10
ns
ns
-
-
10
ns
[1]
5
-
+10
ns
[1]
5
-
+10
ns
5
-
-
+5
-
ns
ns
[2][3]
(T
cy(CCLK)
×
(2 + WST1)) +
(
20)
[2][3]
(T
cy(CCLK)
×
(2 + WST1)) +
(
20)
[2][4]
T
cy(CCLK)
+ (
20)
t
am(ibr)
memory access time (initial
burst-ROM)
memory access time
(subsequent burst-ROM)
data hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
XCLK HIGH to OE LOW time
XCLK HIGH to OE HIGH
time
Write cycle parameters
t
AVCSL
address valid to CS LOW
time
t
CSLDV
CS LOW to data valid time
t
CSLWEL
CS LOW to WE LOW time
t
CSLBLSL
CS LOW to BLS LOW time
t
WELDV
WE LOW to data valid time
t
CSLDV
CS LOW to data valid time
t
WELWEH
WE LOW to WE HIGH time
-
-
ns
t
am(sbr)
-
-
ns
t
h(D)
t
CSHOEH
t
OEHANV
[5]
0
-
-
-
-
+5
+5
ns
ns
ns
5
5
t
CHOEL
t
CHOEH
5
5
-
-
+5
+5
ns
ns
[1]
T
cy(CCLK)
10
-
-
ns
5
5
5
5
5
-
-
-
-
-
-
+5
+5
+5
+5
+5
T
cy(CCLK)
×
(1 +
WST2) + 5
T
cy(CCLK)
×
(1 + WST2) + 5
T
cy(CCLK)
+ 5
ns
ns
ns
ns
ns
ns
[2]
T
cy(CCLK)
×
(1 + WST2)
5
t
BLSLBLSH
BLS LOW to BLS HIGH time
[2]
T
cy(CCLK)
×
(1 + WST2)
5
-
ns
t
WEHANV
WE HIGH to address invalid
time
WE HIGH to data invalid time
BLS HIGH to address invalid
time
[2]
T
cy(CCLK)
5
-
ns
t
WEHDNV
t
BLSHANV
[2]
(2
×
T
cy(CCLK)
)
5
[2]
T
cy(CCLK)
5
-
-
(2
×
T
cy(CCLK)
) + 5
T
cy(CCLK)
+ 5
ns
ns
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