參數資料
型號： LPC2364FBD100
廠商： NXP Semiconductors N.V.
元件分類： 數學處理器
英文描述： ARM7 with 128 kB flash, 34 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC
封裝： LPC2364FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數： 49/69頁
文件大?。?/td> 517K
代理商： LPC2364FBD100
LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 20 October 2011
49 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
11.1 Internal oscillators
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply voltages.
11.2 I/O pins
[1]
Applies to standard I/O pins and RESET pin.
11.3 USB interface
[1]
Characterized but not implemented as production test. Guaranteed by design.
Table 10.
T
amb
=
40
C to +85
C; 3.0 V
V
DD(3V3)
3.6 V.
[1]
Symbol
Parameter
f
osc(RC)
internal RC oscillator frequency
f
i(RTC)
RTC input frequency
Dynamic characteristic: internal oscillators
Conditions
-
-
Min
3.96
-
Typ
[2]
4.02
32.768
Max
4.04
-
Unit
MHz
kHz
Table 11.
T
amb
=
40
C to +85
C; V
DD(3V3)
over specified ranges.
Symbol
Parameter
t
r
rise time
t
f
fall time
Dynamic characteristic: I/O pins
[1]
Conditions
pin configured as output
pin configured as output
Min
3.0
2.5
Typ
-
-
Max
5.0
5.0
Unit
ns
ns
Table 12.
C
L
= 50 pF; R
pu
= 1.5 k
on D+ to V
DD(3V3)
, unless otherwise specified.
Symbol
Parameter
t
r
rise time
t
f
fall time
t
FRFM
differential rise and fall time
matching
V
CRS
output signal crossover voltage
t
FEOPT
source SE0 interval of EOP
t
FDEOP
source jitter for differential transition
to SE0 transition
t
JR1
receiver jitter to next transition
t
JR2
receiver jitter for paired transitions
t
EOPR1
EOP width at receiver
Dynamic characteristics of USB pins (full-speed) (LPC2364/66/68 only)
Conditions
10 % to 90 %
10 % to 90 %
t
r
/ t
f
Min
8.5
7.7
-
Typ
-
-
-
Max
13.8
13.7
109
Unit
ns
ns
%
1.3
160
2
-
-
-
2.0
175
+5
V
ns
ns
see
Figure 14
see
Figure 14
18.5
9
-
-
-
+18.5
+9
-
ns
ns
ns
10 % to 90 %
must reject as
EOP; see
Figure 14
must accept as
EOP; see
Figure 14
[1]
40
t
EOPR2
EOP width at receiver
[1]
82
-
-
ns
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