參數(shù)資料
型號(hào)： LPC2364FBD100
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： ARM7 with 128 kB flash, 34 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC
封裝： LPC2364FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁(yè)數(shù)： 29/69頁(yè)
文件大?。?/td> 517K
代理商： LPC2364FBD100
LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 20 October 2011
29 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
7.20 General purpose 32-bit timers/external event counters
The LPC2364/65/66/67/68 include four 32-bit Timer/Counters. The Timer/Counter is
designed to count cycles of the system derived clock or an externally-supplied clock. It
can optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. The Timer/Counter also includes two capture inputs to trap
the timer value when an input signal transitions, optionally generating an interrupt.
7.20.1
Features
A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Counter or Timer operation.
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four 32-bit match registers that allow:
–
Continuous operation with optional interrupt generation on match.
–
Stop timer on match with optional interrupt generation.
–
Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
–
Set LOW on match.
–
Set HIGH on match.
–
Toggle on match.
–
Do nothing on match.
7.21 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2364/65/66/67/68. The Timer is designed
to count cycles of the system derived clock and optionally switch pins, generate interrupts
or perform other actions when specified timer values occur, based on seven match
registers. The PWM function is in addition to these features, and is based on match
register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
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