參數(shù)資料
型號: LPC2210FBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 16-32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface
中文描述: 16/32位的ARM微控制器;閃存less,10位ADC和外部存儲器接口
封裝: LPC2210FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2220FBD144<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.
文件頁數(shù): 39/50頁
文件大?。?/td> 259K
代理商: LPC2210FBD144
LPC2210_2220_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
39 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
[1]
Except on initial access, in which case the address is set up T
cy(CCLK)
earlier.
T
cy(CCLK)
=
1
CCLK
.
Latest of address valid, CS LOW, OE LOW to data valid.
[2]
[3]
[4]
See the LPC2210/20 user manual UM10114_1for a description of the WSTn bits.
[5]
Address valid to data valid.
[6]
Earliest of CS HIGH, OE HIGH, address change to data invalid.
t
BLSHDNV
BLS HIGH to data invalid
time
XCLK HIGH to data valid
time
XCLK HIGH to WE LOW time
XCLK HIGH to BLS LOW
time
XCLK HIGH to WE HIGH
time
XCLK HIGH to BLS HIGH
time
XCLK HIGH to data invalid
time
[2]
(2
×
T
cy(CCLK)
)
5
-
(2
×
T
cy(CCLK)
) + 5
ns
t
CHDV
-
-
10
ns
t
CHWEL
t
CHBLSL
-
-
-
-
10
10
ns
ns
t
CHWEH
-
-
10
ns
t
CHBLSH
-
-
10
ns
t
CHDNV
-
-
10
ns
Table 14.
C
L
= 25 pF; T
amb
= 40
°
C.
Symbol
Parameter
External memory interface dynamic characteristics
…continued
Conditions
Min
Typ Max
Unit
Table 15.
Access cycle
Standard read access specifications
Max frequency
WST setting
WST
0; round up to
integer
Memory access time requirement
standard read
standard write
burst read - initial
burst read - subsequent 3
×
N/A
f
MAX
RAM
--------------------------------
WST1
t
cy CCLK
20 ns
+
)
--------------------------------
2
t
RAM
t
cy CCLK
)
2
WST1
+
(
)
×
20 ns
f
MAX
WRITE
---------------------------------
WST2
t
-------------------------------------------
t
5
+
t
cy CCLK
)
t
WRITE
t
cy CCLK
)
1
WST2
+
(
)
×
5 ns
f
MAX
20 ns
+
t
INIT
-------------------------------
WST1
t
t
cy CCLK
)
--------------------------------
2
t
INIT
t
cy CCLK
)
2
WST1
+
(
)
×
20 ns
f
MAX
ROM
--------------------------------
t
ROM
t
cy CCLK
)
20 ns
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